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| author | Michael Brown | 2021-05-12 11:24:00 +0200 |
|---|---|---|
| committer | Michael Brown | 2021-05-12 11:24:00 +0200 |
| commit | 05fcf1a2f0809b8d87ca5affea1f1bfe0996235b (patch) | |
| tree | bfa6c7eb41d6f0879f2fa33f7926d30f480fedbe /src/arch/x86/include/ipxe | |
| parent | [prefix] Specify i486 architecture for LZMA decompressor (diff) | |
| download | ipxe-05fcf1a2f0809b8d87ca5affea1f1bfe0996235b.tar.gz ipxe-05fcf1a2f0809b8d87ca5affea1f1bfe0996235b.tar.xz ipxe-05fcf1a2f0809b8d87ca5affea1f1bfe0996235b.zip | |
[rng] Check for TSC support before using RTC entropy source
Signed-off-by: Michael Brown <mcb30@ipxe.org>
Diffstat (limited to 'src/arch/x86/include/ipxe')
| -rw-r--r-- | src/arch/x86/include/ipxe/cpuid.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/arch/x86/include/ipxe/cpuid.h b/src/arch/x86/include/ipxe/cpuid.h index b5403bd9d..3983dfb89 100644 --- a/src/arch/x86/include/ipxe/cpuid.h +++ b/src/arch/x86/include/ipxe/cpuid.h @@ -42,6 +42,9 @@ struct x86_features { /** Hypervisor is present */ #define CPUID_FEATURES_INTEL_ECX_HYPERVISOR 0x80000000UL +/** TSC is present */ +#define CPUID_FEATURES_INTEL_EDX_TSC 0x00000010UL + /** FXSAVE and FXRSTOR are supported */ #define CPUID_FEATURES_INTEL_EDX_FXSR 0x01000000UL |