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| author | Michael Brown | 2021-02-13 00:22:54 +0100 |
|---|---|---|
| committer | Michael Brown | 2021-02-13 00:22:54 +0100 |
| commit | c160fb259378e5f08190db39b5bf4f697f892e7c (patch) | |
| tree | 371560e395c41d4f48eeeb5200ff7af4344f5fcd /src/arch/x86/interface/pxe | |
| parent | [build] Remove support for building with the Intel C compiler (diff) | |
| download | ipxe-c160fb259378e5f08190db39b5bf4f697f892e7c.tar.gz ipxe-c160fb259378e5f08190db39b5bf4f697f892e7c.tar.xz ipxe-c160fb259378e5f08190db39b5bf4f697f892e7c.zip | |
[build] Use .balign directive instead of .align
The semantics of the assembler's .align directive vary by CPU
architecture. For the ARM builds, it specifies a power of two rather
than a number of bytes. This currently leads to the .einfo entries
(which do not appear in the final binary) having an alignment of 256
bytes for the ARM builds.
Fix by switching to the GNU-specific directive .balign, which is
consistent across architectures
Signed-off-by: Michael Brown <mcb30@ipxe.org>
Diffstat (limited to 'src/arch/x86/interface/pxe')
| -rw-r--r-- | src/arch/x86/interface/pxe/pxe_entry.S | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/arch/x86/interface/pxe/pxe_entry.S b/src/arch/x86/interface/pxe/pxe_entry.S index 663aa842e..3a5a100e3 100644 --- a/src/arch/x86/interface/pxe/pxe_entry.S +++ b/src/arch/x86/interface/pxe/pxe_entry.S @@ -34,7 +34,7 @@ FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL ) */ .section ".text16.data", "aw", @progbits .globl ppxe - .align 16 + .balign 16 ppxe: .ascii "!PXE" /* Signature */ .byte pxe_length /* StructLength */ @@ -72,7 +72,7 @@ undiheader: */ .section ".text16.data", "aw", @progbits .globl pxenv - .align 16 + .balign 16 pxenv: .ascii "PXENV+" /* Signature */ .word 0x0201 /* Version */ |