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| author | Michael Brown | 2021-02-13 00:22:54 +0100 |
|---|---|---|
| committer | Michael Brown | 2021-02-13 00:22:54 +0100 |
| commit | c160fb259378e5f08190db39b5bf4f697f892e7c (patch) | |
| tree | 371560e395c41d4f48eeeb5200ff7af4344f5fcd /src/arch/x86/transitions/librm.S | |
| parent | [build] Remove support for building with the Intel C compiler (diff) | |
| download | ipxe-c160fb259378e5f08190db39b5bf4f697f892e7c.tar.gz ipxe-c160fb259378e5f08190db39b5bf4f697f892e7c.tar.xz ipxe-c160fb259378e5f08190db39b5bf4f697f892e7c.zip | |
[build] Use .balign directive instead of .align
The semantics of the assembler's .align directive vary by CPU
architecture. For the ARM builds, it specifies a power of two rather
than a number of bytes. This currently leads to the .einfo entries
(which do not appear in the final binary) having an alignment of 256
bytes for the ARM builds.
Fix by switching to the GNU-specific directive .balign, which is
consistent across architectures
Signed-off-by: Michael Brown <mcb30@ipxe.org>
Diffstat (limited to 'src/arch/x86/transitions/librm.S')
| -rw-r--r-- | src/arch/x86/transitions/librm.S | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/arch/x86/transitions/librm.S b/src/arch/x86/transitions/librm.S index 9d3eff95..f2fa8c50 100644 --- a/src/arch/x86/transitions/librm.S +++ b/src/arch/x86/transitions/librm.S @@ -99,7 +99,7 @@ FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL ) **************************************************************************** */ .section ".data16.gdt", "aw", @progbits - .align 16 + .balign 16 gdt: gdtr: /* The first GDT entry is unused, the GDTR can fit here. */ gdt_limit: .word gdt_length - 1 @@ -224,7 +224,7 @@ RC_TMP_END: /* Shared temporary static buffer */ .section ".bss16.rm_tmpbuf", "aw", @nobits - .align 16 + .balign 16 rm_tmpbuf: .space VC_TMP_END .size rm_tmpbuf, . - rm_tmpbuf @@ -1470,7 +1470,7 @@ interrupt_wrapper: **************************************************************************** */ .section ".pages", "aw", @nobits - .align SIZEOF_PT + .balign SIZEOF_PT /* Page map level 4 entries (PML4Es) * |