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authorSimon Rettberg2024-04-12 14:00:15 +0200
committerSimon Rettberg2024-04-12 14:00:15 +0200
commit98dc341428e247141f120d05fac48c4e144a4c0f (patch)
tree3ebacb37927e338383ac64c2e20eb0b2f820cb85 /src/include/ipxe/efi/Protocol/DebugSupport.h
parentMerge branch 'master' into openslx (diff)
parentMerge branch 'ipxe:master' into aqc1xx (diff)
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Merge branch 'aqc1xx' into openslx
Diffstat (limited to 'src/include/ipxe/efi/Protocol/DebugSupport.h')
-rw-r--r--src/include/ipxe/efi/Protocol/DebugSupport.h14
1 files changed, 14 insertions, 0 deletions
diff --git a/src/include/ipxe/efi/Protocol/DebugSupport.h b/src/include/ipxe/efi/Protocol/DebugSupport.h
index 453ea975..8f930e33 100644
--- a/src/include/ipxe/efi/Protocol/DebugSupport.h
+++ b/src/include/ipxe/efi/Protocol/DebugSupport.h
@@ -685,6 +685,20 @@ typedef struct {
//
// LoongArch processor exception types.
//
+// The exception types is located in the CSR ESTAT
+// register offset 16 bits, width 6 bits.
+//
+// If you want to register an exception hook, you can
+// shfit the number left by 16 bits, and the exception
+// handler will know the types.
+//
+// For example:
+// mCpu->CpuRegisterInterruptHandler (
+// mCpu,
+// (EXCEPT_LOONGARCH_PPI << CSR_ESTAT_EXC_SHIFT),
+// PpiExceptionHandler
+// );
+//
#define EXCEPT_LOONGARCH_INT 0
#define EXCEPT_LOONGARCH_PIL 1
#define EXCEPT_LOONGARCH_PIS 2