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author | Michael Brown | 2019-04-22 15:43:23 +0200 |
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committer | Michael Brown | 2019-04-24 12:41:38 +0200 |
commit | afee77d816f42c7e405c065395c6a7f4dc2aade1 (patch) | |
tree | d7a248ae2c5039622e5bbbee98fb31d0b65e7fc0 /src/include/ipxe/errfile.h | |
parent | [intel] Add PCI ID for I219-V and -LM 6 to 9 (diff) | |
download | ipxe-afee77d816f42c7e405c065395c6a7f4dc2aade1.tar.gz ipxe-afee77d816f42c7e405c065395c6a7f4dc2aade1.tar.xz ipxe-afee77d816f42c7e405c065395c6a7f4dc2aade1.zip |
[pci] Add support for PCI MSI-X interrupts
The Intel 40 Gigabit Ethernet virtual functions support only MSI-X
interrupts, and will write back completed interrupt descriptors only
when the device attempts to raise an interrupt (or when a complete
cacheline of receive descriptors has been completed).
We cannot actually use MSI-X interrupts within iPXE, since we never
have ownership of the APIC. However, an MSI-X interrupt is
fundamentally just a DMA write of a single dword to an arbitrary
address. We can therefore configure the device to "raise" an
interrupt by writing a meaningless value to an otherwise unused memory
location: this is sufficient to trigger the receive descriptor
writeback logic.
Signed-off-by: Michael Brown <mcb30@ipxe.org>
Diffstat (limited to 'src/include/ipxe/errfile.h')
-rw-r--r-- | src/include/ipxe/errfile.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/include/ipxe/errfile.h b/src/include/ipxe/errfile.h index ce67fc66..02e13d11 100644 --- a/src/include/ipxe/errfile.h +++ b/src/include/ipxe/errfile.h @@ -205,6 +205,7 @@ FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL ); #define ERRFILE_ena ( ERRFILE_DRIVER | 0x00c90000 ) #define ERRFILE_icplus ( ERRFILE_DRIVER | 0x00ca0000 ) #define ERRFILE_intelxl ( ERRFILE_DRIVER | 0x00cb0000 ) +#define ERRFILE_pcimsix ( ERRFILE_DRIVER | 0x00cc0000 ) #define ERRFILE_aoe ( ERRFILE_NET | 0x00000000 ) #define ERRFILE_arp ( ERRFILE_NET | 0x00010000 ) |