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authorMichael Brown2019-04-22 15:43:23 +0200
committerMichael Brown2019-04-24 12:41:38 +0200
commitafee77d816f42c7e405c065395c6a7f4dc2aade1 (patch)
treed7a248ae2c5039622e5bbbee98fb31d0b65e7fc0 /src/net
parent[intel] Add PCI ID for I219-V and -LM 6 to 9 (diff)
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[pci] Add support for PCI MSI-X interrupts
The Intel 40 Gigabit Ethernet virtual functions support only MSI-X interrupts, and will write back completed interrupt descriptors only when the device attempts to raise an interrupt (or when a complete cacheline of receive descriptors has been completed). We cannot actually use MSI-X interrupts within iPXE, since we never have ownership of the APIC. However, an MSI-X interrupt is fundamentally just a DMA write of a single dword to an arbitrary address. We can therefore configure the device to "raise" an interrupt by writing a meaningless value to an otherwise unused memory location: this is sufficient to trigger the receive descriptor writeback logic. Signed-off-by: Michael Brown <mcb30@ipxe.org>
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