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| author | Michael Brown | 2021-05-12 11:24:00 +0200 |
|---|---|---|
| committer | Michael Brown | 2021-05-12 11:24:00 +0200 |
| commit | 05fcf1a2f0809b8d87ca5affea1f1bfe0996235b (patch) | |
| tree | bfa6c7eb41d6f0879f2fa33f7926d30f480fedbe /src | |
| parent | [prefix] Specify i486 architecture for LZMA decompressor (diff) | |
| download | ipxe-05fcf1a2f0809b8d87ca5affea1f1bfe0996235b.tar.gz ipxe-05fcf1a2f0809b8d87ca5affea1f1bfe0996235b.tar.xz ipxe-05fcf1a2f0809b8d87ca5affea1f1bfe0996235b.zip | |
[rng] Check for TSC support before using RTC entropy source
Signed-off-by: Michael Brown <mcb30@ipxe.org>
Diffstat (limited to 'src')
| -rw-r--r-- | src/arch/x86/include/ipxe/cpuid.h | 3 | ||||
| -rw-r--r-- | src/arch/x86/interface/pcbios/rtc_entropy.c | 11 |
2 files changed, 14 insertions, 0 deletions
diff --git a/src/arch/x86/include/ipxe/cpuid.h b/src/arch/x86/include/ipxe/cpuid.h index b5403bd9d..3983dfb89 100644 --- a/src/arch/x86/include/ipxe/cpuid.h +++ b/src/arch/x86/include/ipxe/cpuid.h @@ -42,6 +42,9 @@ struct x86_features { /** Hypervisor is present */ #define CPUID_FEATURES_INTEL_ECX_HYPERVISOR 0x80000000UL +/** TSC is present */ +#define CPUID_FEATURES_INTEL_EDX_TSC 0x00000010UL + /** FXSAVE and FXRSTOR are supported */ #define CPUID_FEATURES_INTEL_EDX_FXSR 0x01000000UL diff --git a/src/arch/x86/interface/pcbios/rtc_entropy.c b/src/arch/x86/interface/pcbios/rtc_entropy.c index e9e6baa59..e0c175685 100644 --- a/src/arch/x86/interface/pcbios/rtc_entropy.c +++ b/src/arch/x86/interface/pcbios/rtc_entropy.c @@ -36,6 +36,7 @@ FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL ); #include <biosint.h> #include <pic8259.h> #include <rtc.h> +#include <ipxe/cpuid.h> #include <ipxe/entropy.h> /** Maximum time to wait for an RTC interrupt, in milliseconds */ @@ -174,8 +175,17 @@ static int rtc_entropy_check ( void ) { * @ret rc Return status code */ static int rtc_entropy_enable ( void ) { + struct x86_features features; int rc; + /* Check that TSC is supported */ + x86_features ( &features ); + if ( ! ( features.intel.edx & CPUID_FEATURES_INTEL_EDX_TSC ) ) { + DBGC ( &rtc_flag, "RTC has no TSC\n" ); + rc = -ENOTSUP; + goto err_no_tsc; + } + /* Hook ISR and enable RTC interrupts */ rtc_hook_isr(); enable_irq ( RTC_IRQ ); @@ -191,6 +201,7 @@ static int rtc_entropy_enable ( void ) { rtc_disable_int(); disable_irq ( RTC_IRQ ); rtc_unhook_isr(); + err_no_tsc: return rc; } |