25 files changed, 3074 insertions, 856 deletions

diff --git a/src/drivers/net/3c515.c b/src/drivers/net/3c515.c
index 7fcc9f0fe..c87495006 100644
--- a/src/drivers/net/3c515.c
+++ b/src/drivers/net/3c515.c
@@ -61,10 +61,6 @@ static void t3c515_wait(unsigned int nticks)
 
 /* TJL definations */
 #define HZ      100
-#define u16 unsigned short
-#define u32 unsigned long
-#define s16 signed short
-#define s32 signed long
 static int if_port;
 static struct corkscrew_private *vp;
 /* Brought directly from 3c515.c by Becker */
diff --git a/src/drivers/net/amd8111e.c b/src/drivers/net/amd8111e.c
new file mode 100644
index 000000000..611cbc854
--- /dev/null
+++ b/src/drivers/net/amd8111e.c
@@ -0,0 +1,681 @@
+/* Advanced  Micro Devices Inc. AMD8111E Linux Network Driver 
+ * Copyright (C) 2004 Advanced Micro Devices 
+ * Copyright (C) 2005 Liu Tao <liutao1980@gmail.com> [etherboot port]
+ * 
+ * Copyright 2001,2002 Jeff Garzik <jgarzik@mandrakesoft.com> [ 8139cp.c,tg3.c ]
+ * Copyright (C) 2001, 2002 David S. Miller (davem@redhat.com)[ tg3.c]
+ * Copyright 1996-1999 Thomas Bogendoerfer [ pcnet32.c ]
+ * Derived from the lance driver written 1993,1994,1995 by Donald Becker.
+ * Copyright 1993 United States Government as represented by the
+ *	Director, National Security Agency.[ pcnet32.c ]
+ * Carsten Langgaard, carstenl@mips.com [ pcnet32.c ]
+ * Copyright (C) 2000 MIPS Technologies, Inc.  All rights reserved.
+ *
+ * 
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 
+ * USA
+ */
+
+#include "etherboot.h"
+#include "nic.h"
+#include "mii.h"
+#include "pci.h"
+#include "timer.h"
+#include "string.h"
+#include "stdint.h"
+#include "amd8111e.h"
+
+
+/* driver definitions */
+#define NUM_TX_SLOTS	2
+#define NUM_RX_SLOTS	4
+#define TX_SLOTS_MASK	1
+#define RX_SLOTS_MASK	3
+
+#define TX_BUF_LEN	1536
+#define RX_BUF_LEN	1536
+
+#define TX_PKT_LEN_MAX	(ETH_FRAME_LEN - ETH_HLEN)
+#define RX_PKT_LEN_MIN	60
+#define RX_PKT_LEN_MAX	ETH_FRAME_LEN
+
+#define TX_TIMEOUT	3000
+#define TX_PROCESS_TIME	10
+#define TX_RETRY	(TX_TIMEOUT / TX_PROCESS_TIME)
+
+#define PHY_RW_RETRY	10
+
+
+struct amd8111e_tx_desc {
+	u16 buf_len;
+	u16 tx_flags;
+	u16 tag_ctrl_info;
+	u16 tag_ctrl_cmd;
+	u32 buf_phy_addr;
+	u32 reserved;
+}; 
+
+struct amd8111e_rx_desc {
+	u32 reserved;
+	u16 msg_len;
+	u16 tag_ctrl_info; 
+	u16 buf_len;
+	u16 rx_flags;
+	u32 buf_phy_addr;
+};
+
+struct eth_frame {
+	u8 dst_addr[ETH_ALEN];
+	u8 src_addr[ETH_ALEN];
+	u16 type;
+	u8 data[ETH_FRAME_LEN - ETH_HLEN];
+} __attribute__((packed));
+
+struct amd8111e_priv {
+	struct amd8111e_tx_desc tx_ring[NUM_TX_SLOTS];
+	struct amd8111e_rx_desc rx_ring[NUM_RX_SLOTS];
+	unsigned char tx_buf[NUM_TX_SLOTS][TX_BUF_LEN];
+	unsigned char rx_buf[NUM_RX_SLOTS][RX_BUF_LEN];
+	unsigned long tx_idx, rx_idx;
+	int tx_consistent;
+
+	char opened;
+	char link;
+	char speed;
+	char duplex;
+	int ext_phy_addr;
+	u32 ext_phy_id;
+
+	struct pci_device *pdev;
+	struct nic *nic;
+	void *mmio;
+};
+
+static struct amd8111e_priv amd8111e;
+
+
+/********************************************************
+ * 		locale functions			*
+ ********************************************************/
+static void amd8111e_init_hw_default(struct amd8111e_priv *lp);
+static int amd8111e_start(struct amd8111e_priv *lp);
+static int amd8111e_read_phy(struct amd8111e_priv *lp, int phy_addr, int reg, u32 *val);
+#if 0
+static int amd8111e_write_phy(struct amd8111e_priv *lp, int phy_addr, int reg, u32 val);
+#endif
+static void amd8111e_probe_ext_phy(struct amd8111e_priv *lp);
+static void amd8111e_disable_interrupt(struct amd8111e_priv *lp);
+static void amd8111e_enable_interrupt(struct amd8111e_priv *lp);
+static void amd8111e_force_interrupt(struct amd8111e_priv *lp);
+static int amd8111e_get_mac_address(struct amd8111e_priv *lp);
+static int amd8111e_init_rx_ring(struct amd8111e_priv *lp);
+static int amd8111e_init_tx_ring(struct amd8111e_priv *lp);
+static int amd8111e_wait_tx_ring(struct amd8111e_priv *lp, unsigned int index);
+static void amd8111e_wait_link(struct amd8111e_priv *lp);
+static void amd8111e_poll_link(struct amd8111e_priv *lp);
+static void amd8111e_restart(struct amd8111e_priv *lp);
+
+
+/* 
+ * This function clears necessary the device registers. 
+ */	
+static void amd8111e_init_hw_default(struct amd8111e_priv *lp)
+{
+	unsigned int reg_val;
+	unsigned int logic_filter[2] = {0,};
+	void *mmio = lp->mmio;
+
+        /* stop the chip */
+	writel(RUN, mmio + CMD0);
+
+	/* Clear RCV_RING_BASE_ADDR */
+	writel(0, mmio + RCV_RING_BASE_ADDR0);
+
+	/* Clear XMT_RING_BASE_ADDR */
+	writel(0, mmio + XMT_RING_BASE_ADDR0);
+	writel(0, mmio + XMT_RING_BASE_ADDR1);
+	writel(0, mmio + XMT_RING_BASE_ADDR2);
+	writel(0, mmio + XMT_RING_BASE_ADDR3);
+
+	/* Clear CMD0  */
+	writel(CMD0_CLEAR, mmio + CMD0);
+	
+	/* Clear CMD2 */
+	writel(CMD2_CLEAR, mmio + CMD2);
+
+	/* Clear CMD7 */
+	writel(CMD7_CLEAR, mmio + CMD7);
+
+	/* Clear DLY_INT_A and DLY_INT_B */
+	writel(0x0, mmio + DLY_INT_A);
+	writel(0x0, mmio + DLY_INT_B);
+
+	/* Clear FLOW_CONTROL */
+	writel(0x0, mmio + FLOW_CONTROL);
+
+	/* Clear INT0  write 1 to clear register */
+	reg_val = readl(mmio + INT0);
+	writel(reg_val, mmio + INT0);
+
+	/* Clear STVAL */
+	writel(0x0, mmio + STVAL);
+
+	/* Clear INTEN0 */
+	writel(INTEN0_CLEAR, mmio + INTEN0);
+
+	/* Clear LADRF */
+	writel(0x0, mmio + LADRF);
+
+	/* Set SRAM_SIZE & SRAM_BOUNDARY registers  */
+	writel(0x80010, mmio + SRAM_SIZE);
+
+	/* Clear RCV_RING0_LEN */
+	writel(0x0, mmio +  RCV_RING_LEN0);
+
+	/* Clear XMT_RING0/1/2/3_LEN */
+	writel(0x0, mmio +  XMT_RING_LEN0);
+	writel(0x0, mmio +  XMT_RING_LEN1);
+	writel(0x0, mmio +  XMT_RING_LEN2);
+	writel(0x0, mmio +  XMT_RING_LEN3);
+
+	/* Clear XMT_RING_LIMIT */
+	writel(0x0, mmio + XMT_RING_LIMIT);
+
+	/* Clear MIB */
+	writew(MIB_CLEAR, mmio + MIB_ADDR);
+
+	/* Clear LARF */
+	amd8111e_writeq(*(u64*)logic_filter, mmio + LADRF);
+
+	/* SRAM_SIZE register */
+	reg_val = readl(mmio + SRAM_SIZE);
+	
+	/* Set default value to CTRL1 Register */
+	writel(CTRL1_DEFAULT, mmio + CTRL1);
+
+	/* To avoid PCI posting bug */
+	readl(mmio + CMD2);
+}
+
+/* 
+ * This function initializes the device registers  and starts the device.  
+ */
+static int amd8111e_start(struct amd8111e_priv *lp)
+{
+	struct nic *nic = lp->nic;
+	void *mmio = lp->mmio;
+	int i, reg_val;
+
+	/* stop the chip */
+	writel(RUN, mmio + CMD0);
+
+	/* AUTOPOLL0 Register *//*TBD default value is 8100 in FPS */
+	writew(0x8100 | lp->ext_phy_addr, mmio + AUTOPOLL0);
+
+	/* enable the port manager and set auto negotiation always */
+	writel(VAL1 | EN_PMGR, mmio + CMD3 );
+	writel(XPHYANE | XPHYRST, mmio + CTRL2); 
+
+	/* set control registers */
+	reg_val = readl(mmio + CTRL1);
+	reg_val &= ~XMTSP_MASK;
+	writel(reg_val | XMTSP_128 | CACHE_ALIGN, mmio + CTRL1);
+
+	/* initialize tx and rx ring base addresses */
+	amd8111e_init_tx_ring(lp);
+	amd8111e_init_rx_ring(lp);
+	writel(virt_to_bus(lp->tx_ring), mmio + XMT_RING_BASE_ADDR0);
+	writel(virt_to_bus(lp->rx_ring), mmio + RCV_RING_BASE_ADDR0);
+	writew(NUM_TX_SLOTS, mmio + XMT_RING_LEN0);
+	writew(NUM_RX_SLOTS, mmio + RCV_RING_LEN0);
+	
+	/* set default IPG to 96 */
+	writew(DEFAULT_IPG, mmio + IPG);
+	writew(DEFAULT_IPG - IFS1_DELTA, mmio + IFS1); 
+
+	/* AutoPAD transmit, Retransmit on Underflow */
+	writel(VAL0 | APAD_XMT | REX_RTRY | REX_UFLO, mmio + CMD2);
+	
+	/* JUMBO disabled */
+	writel(JUMBO, mmio + CMD3);
+
+	/* Setting the MAC address to the device */
+	for(i = 0; i < ETH_ALEN; i++)
+		writeb(nic->node_addr[i], mmio + PADR + i); 
+
+	/* set RUN bit to start the chip, interrupt not enabled */
+	writel(VAL2 | RDMD0 | VAL0 | RUN, mmio + CMD0);
+	
+	/* To avoid PCI posting bug */
+	readl(mmio + CMD0);
+	return 0;
+}
+
+/* 
+This function will read the PHY registers.
+*/
+static int amd8111e_read_phy(struct amd8111e_priv *lp, int phy_addr, int reg, u32 *val)
+{
+	void *mmio = lp->mmio;
+	unsigned int reg_val;
+	unsigned int retry = PHY_RW_RETRY;
+
+	reg_val = readl(mmio + PHY_ACCESS);
+	while (reg_val & PHY_CMD_ACTIVE)
+		reg_val = readl(mmio + PHY_ACCESS);
+
+	writel(PHY_RD_CMD | ((phy_addr & 0x1f) << 21) | ((reg & 0x1f) << 16),
+		mmio + PHY_ACCESS);
+	do {
+		reg_val = readl(mmio + PHY_ACCESS);
+		udelay(30);  /* It takes 30 us to read/write data */
+	} while (--retry && (reg_val & PHY_CMD_ACTIVE));
+
+	if (reg_val & PHY_RD_ERR) {
+		*val = 0;
+		return -1;
+	}
+	
+	*val = reg_val & 0xffff;
+	return 0;
+}
+
+/* 
+This function will write into PHY registers. 
+*/
+#if 0
+static int amd8111e_write_phy(struct amd8111e_priv *lp, int phy_addr, int reg, u32 val)
+{
+	void *mmio = lp->mmio;
+	unsigned int reg_val;
+	unsigned int retry = PHY_RW_RETRY;
+
+	reg_val = readl(mmio + PHY_ACCESS);
+	while (reg_val & PHY_CMD_ACTIVE)
+		reg_val = readl(mmio + PHY_ACCESS);
+
+	writel(PHY_WR_CMD | ((phy_addr & 0x1f) << 21) | ((reg & 0x1f) << 16) | val,
+		mmio + PHY_ACCESS);
+	do {
+		reg_val = readl(mmio + PHY_ACCESS);
+		udelay(30);  /* It takes 30 us to read/write the data */
+	} while (--retry && (reg_val & PHY_CMD_ACTIVE));
+	
+	if(reg_val & PHY_RD_ERR)
+		return -1;
+
+	return 0;
+}
+#endif
+
+static void amd8111e_probe_ext_phy(struct amd8111e_priv *lp)
+{
+	int i;
+
+	lp->ext_phy_id = 0;
+	lp->ext_phy_addr = 1;
+	
+	for (i = 0x1e; i >= 0; i--) {
+		u32 id1, id2;
+
+		if (amd8111e_read_phy(lp, i, MII_PHYSID1, &id1))
+			continue;
+		if (amd8111e_read_phy(lp, i, MII_PHYSID2, &id2))
+			continue;
+		lp->ext_phy_id = (id1 << 16) | id2;
+		lp->ext_phy_addr = i;
+		break;
+	}
+
+	if (lp->ext_phy_id)
+		printf("Found MII PHY ID 0x%08x at address 0x%02x\n",
+			lp->ext_phy_id, lp->ext_phy_addr);
+	else
+		printf("Couldn't detect MII PHY, assuming address 0x01\n");
+}
+
+static void amd8111e_disable_interrupt(struct amd8111e_priv *lp)
+{
+	void *mmio = lp->mmio;
+	unsigned int int0;
+
+	writel(INTREN, mmio + CMD0);
+	writel(INTEN0_CLEAR, mmio + INTEN0);
+	int0 = readl(mmio + INT0);
+	writel(int0, mmio + INT0);
+	readl(mmio + INT0);
+}
+
+static void amd8111e_enable_interrupt(struct amd8111e_priv *lp)
+{
+	void *mmio = lp->mmio;
+
+	writel(VAL3 | LCINTEN | VAL1 | TINTEN0 | VAL0 | RINTEN0, mmio + INTEN0);
+	writel(VAL0 | INTREN, mmio + CMD0);
+	readl(mmio + CMD0);
+}
+
+static void amd8111e_force_interrupt(struct amd8111e_priv *lp)
+{
+	void *mmio = lp->mmio;
+
+	writel(VAL0 | UINTCMD, mmio + CMD0);
+	readl(mmio + CMD0);
+}
+
+static int amd8111e_get_mac_address(struct amd8111e_priv *lp)
+{
+	struct nic *nic = lp->nic;
+	void *mmio = lp->mmio;
+	int i;
+
+	/* BIOS should have set mac address to PADR register,
+	 * so we read PADR to get it.
+	 */
+	for (i = 0; i < ETH_ALEN; i++)
+		nic->node_addr[i] = readb(mmio + PADR + i);
+	printf("Ethernet addr: %!\n", nic->node_addr);
+
+	return 0;
+}
+
+static int amd8111e_init_rx_ring(struct amd8111e_priv *lp)
+{
+	int i;
+
+	lp->rx_idx = 0;
+	
+        /* Initilaizing receive descriptors */
+	for (i = 0; i < NUM_RX_SLOTS; i++) {
+		lp->rx_ring[i].buf_phy_addr = cpu_to_le32(virt_to_bus(lp->rx_buf[i]));
+		lp->rx_ring[i].buf_len = cpu_to_le16(RX_BUF_LEN);
+		wmb();
+		lp->rx_ring[i].rx_flags = cpu_to_le16(OWN_BIT);
+	}
+
+	return 0;
+}
+
+static int amd8111e_init_tx_ring(struct amd8111e_priv *lp)
+{
+	int i;
+
+	lp->tx_idx = 0;
+	lp->tx_consistent = 1;
+	
+	/* Initializing transmit descriptors */
+	for (i = 0; i < NUM_TX_SLOTS; i++) {
+		lp->tx_ring[i].tx_flags = 0;
+		lp->tx_ring[i].buf_phy_addr = 0;
+		lp->tx_ring[i].buf_len = 0;
+	}
+
+	return 0;
+}
+
+static int amd8111e_wait_tx_ring(struct amd8111e_priv *lp, unsigned int index)
+{
+	volatile u16 status;
+	int retry = TX_RETRY;
+
+	status = le16_to_cpu(lp->tx_ring[index].tx_flags);
+	while (--retry && (status & OWN_BIT)) {
+		mdelay(TX_PROCESS_TIME);
+		status = le16_to_cpu(lp->tx_ring[index].tx_flags);
+	}
+	if (status & OWN_BIT) {
+		printf("Error: tx slot %d timeout, stat = 0x%x\n", index, status);
+		amd8111e_restart(lp);
+		return -1;
+	}
+
+	return 0;
+}
+
+static void amd8111e_wait_link(struct amd8111e_priv *lp)
+{
+	unsigned int status;
+	u32 reg_val;
+
+	do {
+		/* read phy to update STAT0 register */
+		amd8111e_read_phy(lp, lp->ext_phy_addr, MII_BMCR, &reg_val);
+		amd8111e_read_phy(lp, lp->ext_phy_addr, MII_BMSR, &reg_val);
+		amd8111e_read_phy(lp, lp->ext_phy_addr, MII_ADVERTISE, &reg_val);
+		amd8111e_read_phy(lp, lp->ext_phy_addr, MII_LPA, &reg_val);
+		status = readl(lp->mmio + STAT0);
+	} while (!(status & AUTONEG_COMPLETE) || !(status & LINK_STATS));
+}
+
+static void amd8111e_poll_link(struct amd8111e_priv *lp)
+{
+	unsigned int status, speed;
+	u32 reg_val;
+
+	if (!lp->link) {
+		/* read phy to update STAT0 register */
+		amd8111e_read_phy(lp, lp->ext_phy_addr, MII_BMCR, &reg_val);
+		amd8111e_read_phy(lp, lp->ext_phy_addr, MII_BMSR, &reg_val);
+		amd8111e_read_phy(lp, lp->ext_phy_addr, MII_ADVERTISE, &reg_val);
+		amd8111e_read_phy(lp, lp->ext_phy_addr, MII_LPA, &reg_val);
+		status = readl(lp->mmio + STAT0);
+
+		if (status & LINK_STATS) {
+			lp->link = 1;
+			speed = (status & SPEED_MASK) >> 7;
+			if (speed == PHY_SPEED_100)
+				lp->speed = 1;
+			else
+				lp->speed = 0;
+			if (status & FULL_DPLX)
+				lp->duplex = 1;
+			else
+				lp->duplex = 0;
+
+			printf("Link is up: %s Mbps %s duplex\n",
+				lp->speed ? "100" : "10", lp->duplex ? "full" : "half");
+		}
+	} else {
+		status = readl(lp->mmio + STAT0);
+		if (!(status & LINK_STATS)) {
+			lp->link = 0;
+			printf("Link is down\n");
+		}
+	}
+}
+
+static void amd8111e_restart(struct amd8111e_priv *lp)
+{
+	printf("\nStarting nic...\n");
+	amd8111e_disable_interrupt(lp);
+	amd8111e_init_hw_default(lp);
+	amd8111e_probe_ext_phy(lp);
+	amd8111e_get_mac_address(lp);
+	amd8111e_start(lp);
+
+	printf("Waiting link up...\n");
+	lp->link = 0;
+	amd8111e_wait_link(lp);
+	amd8111e_poll_link(lp);
+}
+
+
+/********************************************************
+ * 		Interface Functions			*
+ ********************************************************/
+
+static void amd8111e_transmit(struct nic *nic, const char *dst_addr,
+		unsigned int type, unsigned int size, const char *packet)
+{
+	struct amd8111e_priv *lp = nic->priv_data;
+	struct eth_frame *frame;
+	unsigned int index;
+
+	/* check packet size */
+	if (size > TX_PKT_LEN_MAX) {
+		printf("amd8111e_transmit(): too large packet, drop\n");
+		return;
+	}
+
+	/* get tx slot */
+	index = lp->tx_idx;
+	if (amd8111e_wait_tx_ring(lp, index))
+		return;
+
+	/* fill frame */
+	frame = (struct eth_frame *)lp->tx_buf[index];
+	memset(frame->data, 0, TX_PKT_LEN_MAX);
+	memcpy(frame->dst_addr, dst_addr, ETH_ALEN);
+	memcpy(frame->src_addr, nic->node_addr, ETH_ALEN);
+	frame->type = htons(type);
+	memcpy(frame->data, packet, size);
+
+	/* start xmit */
+	lp->tx_ring[index].buf_len = cpu_to_le16(ETH_HLEN + size);
+	lp->tx_ring[index].buf_phy_addr = cpu_to_le32(virt_to_bus(frame));
+	wmb();
+	lp->tx_ring[index].tx_flags = 
+		cpu_to_le16(OWN_BIT | STP_BIT | ENP_BIT | ADD_FCS_BIT | LTINT_BIT);
+	writel(VAL1 | TDMD0, lp->mmio + CMD0);
+	readl(lp->mmio + CMD0);
+
+	/* update slot pointer */
+	lp->tx_idx = (lp->tx_idx + 1) & TX_SLOTS_MASK;
+}
+
+static int amd8111e_poll(struct nic *nic, int retrieve)
+{
+	/* return true if there's an ethernet packet ready to read */
+	/* nic->packet should contain data on return */
+	/* nic->packetlen should contain length of data */
+
+	struct amd8111e_priv *lp = nic->priv_data;
+	u16 status, pkt_len;
+	unsigned int index, pkt_ok;
+
+	amd8111e_poll_link(lp);
+
+	index = lp->rx_idx;
+	status = le16_to_cpu(lp->rx_ring[index].rx_flags);
+	pkt_len = le16_to_cpu(lp->rx_ring[index].msg_len) - 4;	/* remove 4bytes FCS */
+	
+	if (status & OWN_BIT)
+		return 0;
+
+	if (status & ERR_BIT)
+		pkt_ok = 0;
+	else if (!(status & STP_BIT))
+		pkt_ok = 0;
+	else if (!(status & ENP_BIT))
+		pkt_ok = 0;
+	else if (pkt_len < RX_PKT_LEN_MIN)
+		pkt_ok = 0;
+	else if (pkt_len > RX_PKT_LEN_MAX)
+		pkt_ok = 0;
+	else
+		pkt_ok = 1;
+
+	if (pkt_ok) {
+		if (!retrieve)
+			return 1;
+		nic->packetlen = pkt_len;
+		memcpy(nic->packet, lp->rx_buf[index], nic->packetlen);
+	}
+
+	lp->rx_ring[index].buf_phy_addr = cpu_to_le32(virt_to_bus(lp->rx_buf[index]));
+	lp->rx_ring[index].buf_len = cpu_to_le16(RX_BUF_LEN);
+	wmb();
+	lp->rx_ring[index].rx_flags = cpu_to_le16(OWN_BIT);
+	writel(VAL2 | RDMD0, lp->mmio + CMD0);
+	readl(lp->mmio + CMD0);
+
+	lp->rx_idx = (lp->rx_idx + 1) & RX_SLOTS_MASK;
+	return pkt_ok;
+}
+
+static void amd8111e_disable(struct nic *nic)
+{
+	struct amd8111e_priv *lp = nic->priv_data;
+
+	/* disable interrupt */
+	amd8111e_disable_interrupt(lp);
+
+	/* stop chip */
+	amd8111e_init_hw_default(lp);
+
+	/* unmap mmio */
+	iounmap(lp->mmio);
+
+	/* update status */
+	lp->opened = 0;
+}
+
+static void amd8111e_irq(struct nic *nic, irq_action_t action)
+{
+	struct amd8111e_priv *lp = nic->priv_data;
+		
+	switch (action) {
+	case DISABLE:
+		amd8111e_disable_interrupt(lp);
+		break;
+	case ENABLE:
+		amd8111e_enable_interrupt(lp);
+		break;
+	case FORCE:
+		amd8111e_force_interrupt(lp);
+		break;
+	}
+}
+
+static struct nic_operations amd8111e_operations = {
+	.connect	= dummy_connect,
+	.poll		= amd8111e_poll,
+	.transmit	= amd8111e_transmit,
+	.irq		= amd8111e_irq,
+};
+
+static int amd8111e_probe(struct nic *nic, struct pci_device *pdev)
+{
+	struct amd8111e_priv *lp = &amd8111e;
+	unsigned long mmio_start, mmio_len;
+
+	pci_fill_nic ( nic, pdev );
+	
+	mmio_start = pci_bar_start(pdev, PCI_BASE_ADDRESS_0);
+	mmio_len = pci_bar_size(pdev, PCI_BASE_ADDRESS_0);
+
+	memset(lp, 0, sizeof(*lp));
+	lp->pdev = pdev;
+	lp->nic = nic;
+	lp->mmio = ioremap(mmio_start, mmio_len);
+	lp->opened = 1;
+	adjust_pci_device(pdev);
+
+	nic->priv_data = lp;
+
+	amd8111e_restart(lp);
+
+	nic->nic_op	= &amd8111e_operations;
+	return 1;
+}
+
+static struct pci_id amd8111e_nics[] = {
+	PCI_ROM(0x1022, 0x7462, "amd8111e",	"AMD8111E"),
+};
+
+PCI_DRIVER ( amd8111e_driver, amd8111e_nics, PCI_NO_CLASS );
+
+DRIVER ( "AMD8111E", nic_driver, pci_driver, amd8111e_driver,
+	 amd8111e_probe, amd8111e_disable );
diff --git a/src/drivers/net/amd8111e.h b/src/drivers/net/amd8111e.h
new file mode 100644
index 000000000..82b8f7a3c
--- /dev/null
+++ b/src/drivers/net/amd8111e.h
@@ -0,0 +1,629 @@
+/*
+ * Advanced  Micro Devices Inc. AMD8111E Linux Network Driver 
+ * Copyright (C) 2003 Advanced Micro Devices 
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 
+ * USA
+
+Module Name:
+
+    amd8111e.h
+
+Abstract:
+	
+ 	 AMD8111 based 10/100 Ethernet Controller driver definitions. 
+
+Environment:
+    
+	Kernel Mode
+
+Revision History:
+ 	3.0.0
+	   Initial Revision.
+	3.0.1
+*/
+
+#ifndef _AMD811E_H
+#define _AMD811E_H
+
+/* Command style register access
+
+Registers CMD0, CMD2, CMD3,CMD7 and INTEN0 uses a write access technique called command style access. It allows the write to selected bits of this register without altering the bits that are not selected. Command style registers are divided into 4 bytes that can be written independently. Higher order bit of each byte is the  value bit that specifies the value that will be written into the selected bits of register. 
+
+eg., if the value 10011010b is written into the least significant byte of a command style register, bits 1,3 and 4 of the register will be set to 1, and the other bits will not be altered. If the value 00011010b is written into the same byte, bits 1,3 and 4 will be cleared to 0 and the other bits will not be altered.
+
+*/
+
+/*  Offset for Memory Mapped Registers. */
+/* 32 bit registers */
+
+#define  ASF_STAT		0x00	/* ASF status register */
+#define CHIPID			0x04	/* Chip ID regsiter */
+#define	MIB_DATA		0x10	/* MIB data register */
+#define MIB_ADDR		0x14	/* MIB address register */
+#define STAT0			0x30	/* Status0 register */
+#define INT0			0x38	/* Interrupt0 register */
+#define INTEN0			0x40	/* Interrupt0  enable register*/
+#define CMD0			0x48	/* Command0 register */
+#define CMD2			0x50	/* Command2 register */
+#define CMD3			0x54	/* Command3 resiter */
+#define CMD7			0x64	/* Command7 register */
+
+#define CTRL1 			0x6C	/* Control1 register */
+#define CTRL2 			0x70	/* Control2 register */
+
+#define XMT_RING_LIMIT		0x7C	/* Transmit ring limit register */
+
+#define AUTOPOLL0		0x88	/* Auto-poll0 register */
+#define AUTOPOLL1		0x8A	/* Auto-poll1 register */
+#define AUTOPOLL2		0x8C	/* Auto-poll2 register */
+#define AUTOPOLL3		0x8E	/* Auto-poll3 register */
+#define AUTOPOLL4		0x90	/* Auto-poll4 register */
+#define	AUTOPOLL5		0x92	/* Auto-poll5 register */
+
+#define AP_VALUE		0x98	/* Auto-poll value register */
+#define DLY_INT_A		0xA8	/* Group A delayed interrupt register */
+#define DLY_INT_B		0xAC	/* Group B delayed interrupt register */
+
+#define FLOW_CONTROL		0xC8	/* Flow control register */
+#define PHY_ACCESS		0xD0	/* PHY access register */
+
+#define STVAL			0xD8	/* Software timer value register */
+
+#define XMT_RING_BASE_ADDR0	0x100	/* Transmit ring0 base addr register */
+#define XMT_RING_BASE_ADDR1	0x108	/* Transmit ring1 base addr register */
+#define XMT_RING_BASE_ADDR2	0x110	/* Transmit ring2 base addr register */
+#define XMT_RING_BASE_ADDR3	0x118	/* Transmit ring2 base addr register */
+
+#define RCV_RING_BASE_ADDR0	0x120	/* Transmit ring0 base addr register */
+
+#define PMAT0			0x190	/* OnNow pattern register0 */
+#define PMAT1			0x194	/* OnNow pattern register1 */
+
+/* 16bit registers */
+
+#define XMT_RING_LEN0		0x140	/* Transmit Ring0 length register */
+#define XMT_RING_LEN1		0x144	/* Transmit Ring1 length register */
+#define XMT_RING_LEN2		0x148 	/* Transmit Ring2 length register */
+#define XMT_RING_LEN3		0x14C	/* Transmit Ring3 length register */
+
+#define RCV_RING_LEN0		0x150	/* Receive Ring0 length register */
+
+#define SRAM_SIZE		0x178	/* SRAM size register */
+#define SRAM_BOUNDARY		0x17A	/* SRAM boundary register */
+
+/* 48bit register */
+
+#define PADR			0x160	/* Physical address register */
+
+#define IFS1			0x18C	/* Inter-frame spacing Part1 register */
+#define IFS			0x18D	/* Inter-frame spacing register */
+#define IPG			0x18E	/* Inter-frame gap register */
+/* 64bit register */
+
+#define LADRF			0x168	/* Logical address filter register */
+
+
+/* Register Bit Definitions */
+typedef enum {
+
+	ASF_INIT_DONE		= (1 << 1),
+	ASF_INIT_PRESENT	= (1 << 0),
+
+}STAT_ASF_BITS; 
+   
+typedef enum {
+
+	MIB_CMD_ACTIVE		= (1 << 15 ),
+	MIB_RD_CMD		= (1 << 13 ),
+	MIB_CLEAR		= (1 << 12 ),
+	MIB_ADDRESS		= (1 << 0) | (1 << 1) | (1 << 2) | (1 << 3)|
+					(1 << 4) | (1 << 5),
+}MIB_ADDR_BITS;
+
+
+typedef enum {
+	
+	PMAT_DET		= (1 << 12),
+	MP_DET		        = (1 << 11),
+	LC_DET			= (1 << 10),
+	SPEED_MASK		= (1 << 9)|(1 << 8)|(1 << 7),
+	FULL_DPLX		= (1 << 6),
+	LINK_STATS		= (1 << 5),
+	AUTONEG_COMPLETE	= (1 << 4),
+	MIIPD			= (1 << 3),
+	RX_SUSPENDED		= (1 << 2),
+	TX_SUSPENDED		= (1 << 1),
+	RUNNING			= (1 << 0),
+
+}STAT0_BITS;
+
+#define PHY_SPEED_10		0x2
+#define PHY_SPEED_100		0x3
+
+/* INT0				0x38, 32bit register */
+typedef enum {
+
+	INTR			= (1 << 31),
+	PCSINT			= (1 << 28), 
+	LCINT			= (1 << 27),
+	APINT5			= (1 << 26),
+	APINT4			= (1 << 25),
+	APINT3			= (1 << 24),
+	TINT_SUM		= (1 << 23),
+	APINT2			= (1 << 22),
+	APINT1			= (1 << 21),
+	APINT0			= (1 << 20),
+	MIIPDTINT		= (1 << 19),
+	MCCINT			= (1 << 17),
+	MREINT			= (1 << 16),
+	RINT_SUM		= (1 << 15),
+	SPNDINT			= (1 << 14),
+	MPINT			= (1 << 13),
+	SINT			= (1 << 12),
+	TINT3			= (1 << 11),
+	TINT2			= (1 << 10),
+	TINT1			= (1 << 9),
+	TINT0			= (1 << 8),
+	UINT			= (1 << 7),
+	STINT			= (1 << 4),
+	RINT0			= (1 << 0),
+
+}INT0_BITS;
+
+typedef enum {
+
+	VAL3			= (1 << 31),   /* VAL bit for byte 3 */
+	VAL2			= (1 << 23),   /* VAL bit for byte 2 */
+	VAL1			= (1 << 15),   /* VAL bit for byte 1 */
+	VAL0			= (1 << 7),    /* VAL bit for byte 0 */
+
+}VAL_BITS;
+
+typedef enum {
+
+	/* VAL3 */
+	LCINTEN			= (1 << 27),
+	APINT5EN		= (1 << 26),
+	APINT4EN		= (1 << 25),
+	APINT3EN		= (1 << 24),
+	/* VAL2 */
+	APINT2EN		= (1 << 22),
+	APINT1EN		= (1 << 21),
+	APINT0EN		= (1 << 20),
+	MIIPDTINTEN		= (1 << 19),
+	MCCIINTEN		= (1 << 18),
+	MCCINTEN		= (1 << 17),
+	MREINTEN		= (1 << 16),
+	/* VAL1 */
+	SPNDINTEN		= (1 << 14),
+	MPINTEN			= (1 << 13),
+	TINTEN3			= (1 << 11),
+	SINTEN			= (1 << 12),
+	TINTEN2			= (1 << 10),
+	TINTEN1			= (1 << 9),
+	TINTEN0			= (1 << 8),
+	/* VAL0 */
+	STINTEN			= (1 << 4),
+	RINTEN0			= (1 << 0),
+
+	INTEN0_CLEAR 		= 0x1F7F7F1F, /* Command style register */
+
+}INTEN0_BITS;		
+
+typedef enum {
+	/* VAL2 */
+	RDMD0			= (1 << 16),
+	/* VAL1 */
+	TDMD3			= (1 << 11),
+	TDMD2			= (1 << 10),
+	TDMD1			= (1 << 9),
+	TDMD0			= (1 << 8),
+	/* VAL0 */
+	UINTCMD			= (1 << 6),
+	RX_FAST_SPND		= (1 << 5),
+	TX_FAST_SPND		= (1 << 4),
+	RX_SPND			= (1 << 3),
+	TX_SPND			= (1 << 2),
+	INTREN			= (1 << 1),
+	RUN			= (1 << 0),
+
+	CMD0_CLEAR 		= 0x000F0F7F,   /* Command style register */	
+
+}CMD0_BITS;
+
+typedef enum {
+
+	/* VAL3 */
+	CONDUIT_MODE		= (1 << 29),
+	/* VAL2 */
+	RPA			= (1 << 19),
+	DRCVPA			= (1 << 18),
+	DRCVBC			= (1 << 17),
+	PROM			= (1 << 16),
+	/* VAL1 */
+	ASTRP_RCV		= (1 << 13),
+	RCV_DROP0	  	= (1 << 12),
+	EMBA			= (1 << 11),
+	DXMT2PD			= (1 << 10),
+	LTINTEN			= (1 << 9),
+	DXMTFCS			= (1 << 8),
+	/* VAL0 */
+	APAD_XMT		= (1 << 6),
+	DRTY			= (1 << 5),
+	INLOOP			= (1 << 4),
+	EXLOOP			= (1 << 3),
+	REX_RTRY		= (1 << 2),
+	REX_UFLO		= (1 << 1),
+	REX_LCOL		= (1 << 0),
+
+	CMD2_CLEAR 		= 0x3F7F3F7F,   /* Command style register */
+
+}CMD2_BITS;
+
+typedef enum {
+
+	/* VAL3 */
+	ASF_INIT_DONE_ALIAS	= (1 << 29),
+	/* VAL2 */
+	JUMBO			= (1 << 21),
+	VSIZE			= (1 << 20),	
+	VLONLY			= (1 << 19),
+	VL_TAG_DEL		= (1 << 18),	
+	/* VAL1 */
+	EN_PMGR			= (1 << 14),			
+	INTLEVEL		= (1 << 13),
+	FORCE_FULL_DUPLEX	= (1 << 12),	
+	FORCE_LINK_STATUS	= (1 << 11),	
+	APEP			= (1 << 10),	
+	MPPLBA			= (1 << 9),	
+	/* VAL0 */
+	RESET_PHY_PULSE		= (1 << 2),	
+	RESET_PHY		= (1 << 1),	
+	PHY_RST_POL		= (1 << 0),	
+
+}CMD3_BITS;
+
+
+typedef enum {
+
+	/* VAL0 */
+	PMAT_SAVE_MATCH		= (1 << 4),
+	PMAT_MODE		= (1 << 3),
+	MPEN_SW			= (1 << 1),
+	LCMODE_SW		= (1 << 0),
+
+	CMD7_CLEAR  		= 0x0000001B	/* Command style register */
+
+}CMD7_BITS;
+
+
+typedef enum {
+
+	RESET_PHY_WIDTH		= (0xF << 16) | (0xF<< 20), /* 0x00FF0000 */
+	XMTSP_MASK		= (1 << 9) | (1 << 8),	/* 9:8 */
+	XMTSP_128		= (1 << 9),	/* 9 */	
+	XMTSP_64		= (1 << 8),
+	CACHE_ALIGN		= (1 << 4),
+	BURST_LIMIT_MASK	= (0xF << 0 ),
+	CTRL1_DEFAULT		= 0x00010111,
+
+}CTRL1_BITS;
+
+typedef enum {
+
+	FMDC_MASK		= (1 << 9)|(1 << 8),	/* 9:8 */
+	XPHYRST			= (1 << 7),
+	XPHYANE			= (1 << 6),
+	XPHYFD			= (1 << 5),
+	XPHYSP			= (1 << 4) | (1 << 3),	/* 4:3 */
+	APDW_MASK		= (1 <<	2) | (1 << 1) | (1 << 0), /* 2:0 */
+
+}CTRL2_BITS;
+
+/* XMT_RING_LIMIT		0x7C, 32bit register */
+typedef enum {
+
+	XMT_RING2_LIMIT		= (0xFF << 16),	/* 23:16 */
+	XMT_RING1_LIMIT		= (0xFF << 8),	/* 15:8 */
+	XMT_RING0_LIMIT		= (0xFF << 0), 	/* 7:0 */
+
+}XMT_RING_LIMIT_BITS;
+
+typedef enum {
+
+	AP_REG0_EN		= (1 << 15),
+	AP_REG0_ADDR_MASK	= (0xF << 8) |(1 << 12),/* 12:8 */
+	AP_PHY0_ADDR_MASK	= (0xF << 0) |(1 << 4),/* 4:0 */
+
+}AUTOPOLL0_BITS;
+
+/* AUTOPOLL1			0x8A, 16bit register */
+typedef enum {
+
+	AP_REG1_EN		= (1 << 15),
+	AP_REG1_ADDR_MASK	= (0xF << 8) |(1 << 12),/* 12:8 */
+	AP_PRE_SUP1		= (1 << 6),
+	AP_PHY1_DFLT		= (1 << 5),
+	AP_PHY1_ADDR_MASK	= (0xF << 0) |(1 << 4),/* 4:0 */
+
+}AUTOPOLL1_BITS;
+
+
+typedef enum {
+
+	AP_REG2_EN		= (1 << 15),
+	AP_REG2_ADDR_MASK	= (0xF << 8) |(1 << 12),/* 12:8 */
+	AP_PRE_SUP2		= (1 << 6),
+	AP_PHY2_DFLT		= (1 << 5),
+	AP_PHY2_ADDR_MASK	= (0xF << 0) |(1 << 4),/* 4:0 */
+
+}AUTOPOLL2_BITS;
+
+typedef enum {
+
+	AP_REG3_EN		= (1 << 15),
+	AP_REG3_ADDR_MASK	= (0xF << 8) |(1 << 12),/* 12:8 */
+	AP_PRE_SUP3		= (1 << 6),
+	AP_PHY3_DFLT		= (1 << 5),
+	AP_PHY3_ADDR_MASK	= (0xF << 0) |(1 << 4),/* 4:0 */
+
+}AUTOPOLL3_BITS;
+
+
+typedef enum {
+
+	AP_REG4_EN		= (1 << 15),
+	AP_REG4_ADDR_MASK	= (0xF << 8) |(1 << 12),/* 12:8 */
+	AP_PRE_SUP4		= (1 << 6),
+	AP_PHY4_DFLT		= (1 << 5),
+	AP_PHY4_ADDR_MASK	= (0xF << 0) |(1 << 4),/* 4:0 */
+
+}AUTOPOLL4_BITS;
+
+
+typedef enum {
+
+	AP_REG5_EN		= (1 << 15),
+	AP_REG5_ADDR_MASK	= (0xF << 8) |(1 << 12),/* 12:8 */
+	AP_PRE_SUP5		= (1 << 6),
+	AP_PHY5_DFLT		= (1 << 5),
+	AP_PHY5_ADDR_MASK	= (0xF << 0) |(1 << 4),/* 4:0 */
+
+}AUTOPOLL5_BITS;
+
+
+
+
+/* AP_VALUE 			0x98, 32bit ragister */
+typedef enum {
+
+	AP_VAL_ACTIVE		= (1 << 31),
+	AP_VAL_RD_CMD		= ( 1 << 29),
+	AP_ADDR			= (1 << 18)|(1 << 17)|(1 << 16), /* 18:16 */
+	AP_VAL			= (0xF << 0) | (0xF << 4) |( 0xF << 8) |
+				  (0xF << 12),	/* 15:0 */
+
+}AP_VALUE_BITS;
+
+typedef enum {
+
+	DLY_INT_A_R3		= (1 << 31),
+	DLY_INT_A_R2		= (1 << 30),
+	DLY_INT_A_R1		= (1 << 29),
+	DLY_INT_A_R0		= (1 << 28),
+	DLY_INT_A_T3		= (1 << 27),
+	DLY_INT_A_T2		= (1 << 26),
+	DLY_INT_A_T1		= (1 << 25),
+	DLY_INT_A_T0		= ( 1 << 24),
+	EVENT_COUNT_A		= (0xF << 16) | (0x1 << 20),/* 20:16 */
+	MAX_DELAY_TIME_A	= (0xF << 0) | (0xF << 4) | (1 << 8)|
+				  (1 << 9) | (1 << 10),	/* 10:0 */
+
+}DLY_INT_A_BITS;
+
+typedef enum {
+
+	DLY_INT_B_R3		= (1 << 31),
+	DLY_INT_B_R2		= (1 << 30),
+	DLY_INT_B_R1		= (1 << 29),
+	DLY_INT_B_R0		= (1 << 28),
+	DLY_INT_B_T3		= (1 << 27),
+	DLY_INT_B_T2		= (1 << 26),
+	DLY_INT_B_T1		= (1 << 25),
+	DLY_INT_B_T0		= ( 1 << 24),
+	EVENT_COUNT_B		= (0xF << 16) | (0x1 << 20),/* 20:16 */
+	MAX_DELAY_TIME_B	= (0xF << 0) | (0xF << 4) | (1 << 8)| 
+				  (1 << 9) | (1 << 10),	/* 10:0 */
+}DLY_INT_B_BITS;
+
+
+/* FLOW_CONTROL 		0xC8, 32bit register */
+typedef enum {
+
+	PAUSE_LEN_CHG		= (1 << 30),
+	FTPE			= (1 << 22),
+	FRPE			= (1 << 21),
+	NAPA			= (1 << 20),
+	NPA			= (1 << 19),
+	FIXP			= ( 1 << 18),
+	FCCMD			= ( 1 << 16),
+	PAUSE_LEN		= (0xF << 0) | (0xF << 4) |( 0xF << 8) |	 				  (0xF << 12),	/* 15:0 */
+
+}FLOW_CONTROL_BITS;
+
+/* PHY_ ACCESS			0xD0, 32bit register */
+typedef enum {
+
+	PHY_CMD_ACTIVE		= (1 << 31),
+	PHY_WR_CMD		= (1 << 30),
+	PHY_RD_CMD		= (1 << 29),
+	PHY_RD_ERR		= (1 << 28),
+	PHY_PRE_SUP		= (1 << 27),
+	PHY_ADDR		= (1 << 21) | (1 << 22) | (1 << 23)|
+				  	(1 << 24) |(1 << 25),/* 25:21 */
+	PHY_REG_ADDR		= (1 << 16) | (1 << 17) | (1 << 18)|	 			  	   	  	(1 << 19) | (1 << 20),/* 20:16 */
+	PHY_DATA		= (0xF << 0)|(0xF << 4) |(0xF << 8)|
+					(0xF << 12),/* 15:0 */
+
+}PHY_ACCESS_BITS;
+
+
+/* PMAT0			0x190,	 32bit register */
+typedef enum {
+	PMR_ACTIVE		= (1 << 31),
+	PMR_WR_CMD		= (1 << 30),
+	PMR_RD_CMD		= (1 << 29),
+	PMR_BANK		= (1 <<28),
+	PMR_ADDR		= (0xF << 16)|(1 << 20)|(1 << 21)|
+				  	(1 << 22),/* 22:16 */
+	PMR_B4			= (0xF << 0) | (0xF << 4),/* 15:0 */
+}PMAT0_BITS;
+
+
+/* PMAT1			0x194,	 32bit register */
+typedef enum {
+	PMR_B3			= (0xF << 24) | (0xF <<28),/* 31:24 */
+	PMR_B2			= (0xF << 16) |(0xF << 20),/* 23:16 */
+	PMR_B1			= (0xF << 8) | (0xF <<12), /* 15:8 */
+	PMR_B0			= (0xF << 0)|(0xF << 4),/* 7:0 */
+}PMAT1_BITS;
+
+/************************************************************************/
+/*                                                                      */
+/*                      MIB counter definitions                         */
+/*                                                                      */
+/************************************************************************/
+
+#define rcv_miss_pkts				0x00
+#define rcv_octets				0x01
+#define rcv_broadcast_pkts			0x02
+#define rcv_multicast_pkts			0x03
+#define rcv_undersize_pkts			0x04
+#define rcv_oversize_pkts			0x05
+#define rcv_fragments				0x06
+#define rcv_jabbers				0x07
+#define rcv_unicast_pkts			0x08
+#define rcv_alignment_errors			0x09
+#define rcv_fcs_errors				0x0A
+#define rcv_good_octets				0x0B
+#define rcv_mac_ctrl				0x0C
+#define rcv_flow_ctrl				0x0D
+#define rcv_pkts_64_octets			0x0E
+#define rcv_pkts_65to127_octets			0x0F
+#define rcv_pkts_128to255_octets		0x10
+#define rcv_pkts_256to511_octets		0x11
+#define rcv_pkts_512to1023_octets		0x12
+#define rcv_pkts_1024to1518_octets		0x13
+#define rcv_unsupported_opcode			0x14
+#define rcv_symbol_errors			0x15
+#define rcv_drop_pkts_ring1			0x16
+#define rcv_drop_pkts_ring2			0x17
+#define rcv_drop_pkts_ring3			0x18
+#define rcv_drop_pkts_ring4			0x19
+#define rcv_jumbo_pkts				0x1A
+
+#define xmt_underrun_pkts			0x20
+#define xmt_octets				0x21
+#define xmt_packets				0x22
+#define xmt_broadcast_pkts			0x23
+#define xmt_multicast_pkts			0x24
+#define xmt_collisions				0x25
+#define xmt_unicast_pkts			0x26
+#define xmt_one_collision			0x27
+#define xmt_multiple_collision			0x28
+#define xmt_deferred_transmit			0x29
+#define xmt_late_collision			0x2A
+#define xmt_excessive_defer			0x2B
+#define xmt_loss_carrier			0x2C
+#define xmt_excessive_collision			0x2D
+#define xmt_back_pressure			0x2E
+#define xmt_flow_ctrl				0x2F
+#define xmt_pkts_64_octets			0x30
+#define xmt_pkts_65to127_octets			0x31
+#define xmt_pkts_128to255_octets		0x32
+#define xmt_pkts_256to511_octets		0x33
+#define xmt_pkts_512to1023_octets		0x34
+#define xmt_pkts_1024to1518_octet		0x35
+#define xmt_oversize_pkts			0x36
+#define xmt_jumbo_pkts				0x37
+
+/* ipg parameters */
+#define DEFAULT_IPG			0x60
+#define IFS1_DELTA			36
+#define	IPG_CONVERGE_JIFFIES (HZ/2)
+#define	IPG_STABLE_TIME	5
+#define	MIN_IPG	96
+#define	MAX_IPG	255
+#define IPG_STEP	16
+#define CSTATE  1 
+#define SSTATE  2 
+
+/* amd8111e decriptor flag definitions */
+typedef enum {
+
+	OWN_BIT		=	(1 << 15),
+	ADD_FCS_BIT	=	(1 << 13),
+	LTINT_BIT	=	(1 << 12),
+	STP_BIT		=	(1 << 9),
+	ENP_BIT		=	(1 << 8),
+	KILL_BIT	= 	(1 << 6),
+	TCC_VLAN_INSERT	=	(1 << 1),
+	TCC_VLAN_REPLACE =	(1 << 1) |( 1<< 0),
+
+}TX_FLAG_BITS;
+
+typedef enum {
+	ERR_BIT 	=	(1 << 14),
+	FRAM_BIT	=  	(1 << 13),
+	OFLO_BIT	=       (1 << 12),
+	CRC_BIT		=	(1 << 11),
+	PAM_BIT		=	(1 << 6),
+	LAFM_BIT	= 	(1 << 5),
+	BAM_BIT		=	(1 << 4),
+	TT_VLAN_TAGGED	= 	(1 << 3) |(1 << 2),/* 0x000 */
+	TT_PRTY_TAGGED	=	(1 << 3),/* 0x0008 */
+
+}RX_FLAG_BITS;
+
+#define RESET_RX_FLAGS		0x0000
+#define TT_MASK			0x000c
+#define TCC_MASK		0x0003
+
+/* driver ioctl parameters */
+#define AMD8111E_REG_DUMP_LEN	 13*sizeof(u32) 
+
+/* crc generator constants */
+#define CRC32 0xedb88320
+#define INITCRC 0xFFFFFFFF
+
+/* kernel provided writeq does not write 64 bits into the amd8111e device register instead writes only higher 32bits data into lower 32bits of the register.
+BUG? */
+#define  amd8111e_writeq(_UlData,_memMap)   \
+		writel(*(u32*)(&_UlData), _memMap);	\
+		writel(*(u32*)((u8*)(&_UlData)+4), _memMap+4)	
+
+/* maps the external speed options to internal value */
+typedef enum {
+	SPEED_AUTONEG,
+	SPEED10_HALF,
+	SPEED10_FULL,
+	SPEED100_HALF,
+	SPEED100_FULL,
+}EXT_PHY_OPTION;
+
+
+#endif /* _AMD8111E_H */
+
diff --git a/src/drivers/net/davicom.c b/src/drivers/net/davicom.c
index fdbf98342..d087e29e7 100644
--- a/src/drivers/net/davicom.c
+++ b/src/drivers/net/davicom.c
@@ -50,13 +50,6 @@
 
 #define TX_TIME_OUT       2*TICKS_PER_SEC
 
-typedef unsigned char  u8;
-typedef   signed char  s8;
-typedef unsigned short u16;
-typedef   signed short s16;
-typedef unsigned int   u32;
-typedef   signed int   s32;
-
 /* Register offsets for davicom device */
 enum davicom_offsets {
    CSR0=0,     CSR1=0x08,  CSR2=0x10,  CSR3=0x18,  CSR4=0x20,  CSR5=0x28,
diff --git a/src/drivers/net/depca.c b/src/drivers/net/depca.c
index 3707da64e..cc904c71e 100644
--- a/src/drivers/net/depca.c
+++ b/src/drivers/net/depca.c
@@ -413,13 +413,6 @@ static char *adapter_name[] = {
 #define ALIGN8      ((u32)8 - 1)       /* 2 longword (quadword) align */
 #define ALIGN         ALIGN8              /* Keep the LANCE happy... */
 
-typedef	long		s32;
-typedef	unsigned long	u32;
-typedef	short		s16;
-typedef	unsigned short	u16;
-typedef	char		s8;
-typedef	unsigned char	u8;
-
 /*
 ** The DEPCA Rx and Tx ring descriptors. 
 */
diff --git a/src/drivers/net/dmfe.c b/src/drivers/net/dmfe.c
index 4061ebfc9..e1ff44ec5 100644
--- a/src/drivers/net/dmfe.c
+++ b/src/drivers/net/dmfe.c
@@ -51,13 +51,6 @@
 #define dprintf(x)
 #endif
 
-typedef unsigned char u8;
-typedef signed char s8;
-typedef unsigned short u16;
-typedef signed short s16;
-typedef unsigned int u32;
-typedef signed int s32;
-
 /* Condensed operations for readability. */
 #define virt_to_le32desc(addr)  cpu_to_le32(virt_to_bus(addr))
 #define le32desc_to_virt(addr)  bus_to_virt(le32_to_cpu(addr))
diff --git a/src/drivers/net/e1000.c b/src/drivers/net/e1000.c
index d5de2cc47..2eb6b333a 100644
--- a/src/drivers/net/e1000.c
+++ b/src/drivers/net/e1000.c
@@ -72,6 +72,9 @@ typedef enum {
  * and the corresponding inplace checks inserted instead.
  * Pieces such as LED handling that we definitely don't need are deleted.
  *
+ * Please keep the function ordering so that it is easy to produce diffs
+ * against the linux driver.
+ *
  * The following defines should not be needed normally,
  * but may be helpful for debugging purposes. */
 
@@ -120,7 +123,9 @@ static int e1000_write_phy_reg_ex(struct e1000_hw *hw, uint32_t reg_addr, uint16
 static void e1000_phy_hw_reset(struct e1000_hw *hw);
 static int e1000_phy_reset(struct e1000_hw *hw);
 static int e1000_detect_gig_phy(struct e1000_hw *hw);
-static void e1000_irq(struct nic *nic, irq_action_t action);
+static int e1000_read_eeprom(struct e1000_hw *hw, uint16_t offset, uint16_t words, uint16_t *data);
+static void e1000_init_rx_addrs(struct e1000_hw *hw);
+static void e1000_clear_vfta(struct e1000_hw *hw);
 
 /* Printing macros... */
 
@@ -174,11 +179,18 @@ static void e1000_irq(struct nic *nic, irq_action_t action);
 
 #define E1000_WRITE_FLUSH(a) {uint32_t x; x = E1000_READ_REG(a, STATUS);}
 
+
+/******************************************************************************
+ * Inline functions from e1000_main.c of the linux driver
+ ******************************************************************************/
+
+#if 0
 static inline uint32_t
 e1000_io_read(struct e1000_hw *hw __unused, uint32_t port)
 {
         return inl(port);
 }
+#endif
 
 static inline void
 e1000_io_write(struct e1000_hw *hw __unused, uint32_t port, uint32_t value)
@@ -197,529 +209,10 @@ static inline void e1000_pci_clear_mwi(struct e1000_hw *hw)
 			      hw->pci_cmd_word & ~PCI_COMMAND_INVALIDATE);
 }
 
-/******************************************************************************
- * Raises the EEPROM's clock input.
- *
- * hw - Struct containing variables accessed by shared code
- * eecd - EECD's current value
- *****************************************************************************/
-static void
-e1000_raise_ee_clk(struct e1000_hw *hw,
-                   uint32_t *eecd)
-{
-	/* Raise the clock input to the EEPROM (by setting the SK bit), and then
-	 * wait <delay> microseconds.
-	 */
-	*eecd = *eecd | E1000_EECD_SK;
-	E1000_WRITE_REG(hw, EECD, *eecd);
-	E1000_WRITE_FLUSH(hw);
-	udelay(hw->eeprom.delay_usec);
-}
-
-/******************************************************************************
- * Lowers the EEPROM's clock input.
- *
- * hw - Struct containing variables accessed by shared code 
- * eecd - EECD's current value
- *****************************************************************************/
-static void
-e1000_lower_ee_clk(struct e1000_hw *hw,
-                   uint32_t *eecd)
-{
-	/* Lower the clock input to the EEPROM (by clearing the SK bit), and then 
-	 * wait 50 microseconds. 
-	 */
-	*eecd = *eecd & ~E1000_EECD_SK;
-	E1000_WRITE_REG(hw, EECD, *eecd);
-	E1000_WRITE_FLUSH(hw);
-	udelay(hw->eeprom.delay_usec);
-}
-
-/******************************************************************************
- * Shift data bits out to the EEPROM.
- *
- * hw - Struct containing variables accessed by shared code
- * data - data to send to the EEPROM
- * count - number of bits to shift out
- *****************************************************************************/
-static void
-e1000_shift_out_ee_bits(struct e1000_hw *hw,
-                        uint16_t data,
-                        uint16_t count)
-{
-	struct e1000_eeprom_info *eeprom = &hw->eeprom;
-	uint32_t eecd;
-	uint32_t mask;
-	
-	/* We need to shift "count" bits out to the EEPROM. So, value in the
-	 * "data" parameter will be shifted out to the EEPROM one bit at a time.
-	 * In order to do this, "data" must be broken down into bits. 
-	 */
-	mask = 0x01 << (count - 1);
-	eecd = E1000_READ_REG(hw, EECD);
-	if (eeprom->type == e1000_eeprom_microwire) {
-		eecd &= ~E1000_EECD_DO;
-	} else if (eeprom->type == e1000_eeprom_spi) {
-		eecd |= E1000_EECD_DO;
-	}
-	do {
-		/* A "1" is shifted out to the EEPROM by setting bit "DI" to a "1",
-		 * and then raising and then lowering the clock (the SK bit controls
-		 * the clock input to the EEPROM).  A "0" is shifted out to the EEPROM
-		 * by setting "DI" to "0" and then raising and then lowering the clock.
-		 */
-		eecd &= ~E1000_EECD_DI;
-		
-		if(data & mask)
-			eecd |= E1000_EECD_DI;
-		
-		E1000_WRITE_REG(hw, EECD, eecd);
-		E1000_WRITE_FLUSH(hw);
-		
-		udelay(eeprom->delay_usec);
-		
-		e1000_raise_ee_clk(hw, &eecd);
-		e1000_lower_ee_clk(hw, &eecd);
-		
-		mask = mask >> 1;
-		
-	} while(mask);
-
-	/* We leave the "DI" bit set to "0" when we leave this routine. */
-	eecd &= ~E1000_EECD_DI;
-	E1000_WRITE_REG(hw, EECD, eecd);
-}
-
-/******************************************************************************
- * Shift data bits in from the EEPROM
- *
- * hw - Struct containing variables accessed by shared code
- *****************************************************************************/
-static uint16_t
-e1000_shift_in_ee_bits(struct e1000_hw *hw,
-                       uint16_t count)
-{
-	uint32_t eecd;
-	uint32_t i;
-	uint16_t data;
-	
-	/* In order to read a register from the EEPROM, we need to shift 'count' 
-	 * bits in from the EEPROM. Bits are "shifted in" by raising the clock
-	 * input to the EEPROM (setting the SK bit), and then reading the value of
-	 * the "DO" bit.  During this "shifting in" process the "DI" bit should
-	 * always be clear.
-	 */
-	
-	eecd = E1000_READ_REG(hw, EECD);
-	
-	eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
-	data = 0;
-	
-	for(i = 0; i < count; i++) {
-		data = data << 1;
-		e1000_raise_ee_clk(hw, &eecd);
-		
-		eecd = E1000_READ_REG(hw, EECD);
-		
-		eecd &= ~(E1000_EECD_DI);
-		if(eecd & E1000_EECD_DO)
-			data |= 1;
-		
-		e1000_lower_ee_clk(hw, &eecd);
-	}
-	
-	return data;
-}
-
-/******************************************************************************
- * Prepares EEPROM for access
- *
- * hw - Struct containing variables accessed by shared code
- *
- * Lowers EEPROM clock. Clears input pin. Sets the chip select pin. This 
- * function should be called before issuing a command to the EEPROM.
- *****************************************************************************/
-static int32_t
-e1000_acquire_eeprom(struct e1000_hw *hw)
-{
-	struct e1000_eeprom_info *eeprom = &hw->eeprom;
-	uint32_t eecd, i=0;
-
-	eecd = E1000_READ_REG(hw, EECD);
-
-	/* Request EEPROM Access */
-	if(hw->mac_type > e1000_82544) {
-		eecd |= E1000_EECD_REQ;
-		E1000_WRITE_REG(hw, EECD, eecd);
-		eecd = E1000_READ_REG(hw, EECD);
-		while((!(eecd & E1000_EECD_GNT)) &&
-		      (i < E1000_EEPROM_GRANT_ATTEMPTS)) {
-			i++;
-			udelay(5);
-			eecd = E1000_READ_REG(hw, EECD);
-		}
-		if(!(eecd & E1000_EECD_GNT)) {
-			eecd &= ~E1000_EECD_REQ;
-			E1000_WRITE_REG(hw, EECD, eecd);
-			DEBUGOUT("Could not acquire EEPROM grant\n");
-			return -E1000_ERR_EEPROM;
-		}
-	}
-
-	/* Setup EEPROM for Read/Write */
-
-	if (eeprom->type == e1000_eeprom_microwire) {
-		/* Clear SK and DI */
-		eecd &= ~(E1000_EECD_DI | E1000_EECD_SK);
-		E1000_WRITE_REG(hw, EECD, eecd);
-
-		/* Set CS */
-		eecd |= E1000_EECD_CS;
-		E1000_WRITE_REG(hw, EECD, eecd);
-	} else if (eeprom->type == e1000_eeprom_spi) {
-		/* Clear SK and CS */
-		eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
-		E1000_WRITE_REG(hw, EECD, eecd);
-		udelay(1);
-	}
-
-	return E1000_SUCCESS;
-}
-
-/******************************************************************************
- * Returns EEPROM to a "standby" state
- * 
- * hw - Struct containing variables accessed by shared code
- *****************************************************************************/
-static void
-e1000_standby_eeprom(struct e1000_hw *hw)
-{
-	struct e1000_eeprom_info *eeprom = &hw->eeprom;
-	uint32_t eecd;
-	
-	eecd = E1000_READ_REG(hw, EECD);
-
-	if(eeprom->type == e1000_eeprom_microwire) {
-
-		/* Deselect EEPROM */
-		eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
-		E1000_WRITE_REG(hw, EECD, eecd);
-		E1000_WRITE_FLUSH(hw);
-		udelay(eeprom->delay_usec);
-	
-		/* Clock high */
-		eecd |= E1000_EECD_SK;
-		E1000_WRITE_REG(hw, EECD, eecd);
-		E1000_WRITE_FLUSH(hw);
-		udelay(eeprom->delay_usec);
-	
-		/* Select EEPROM */
-		eecd |= E1000_EECD_CS;
-		E1000_WRITE_REG(hw, EECD, eecd);
-		E1000_WRITE_FLUSH(hw);
-		udelay(eeprom->delay_usec);
-
-		/* Clock low */
-		eecd &= ~E1000_EECD_SK;
-		E1000_WRITE_REG(hw, EECD, eecd);
-		E1000_WRITE_FLUSH(hw);
-		udelay(eeprom->delay_usec);
-	} else if(eeprom->type == e1000_eeprom_spi) {
-		/* Toggle CS to flush commands */
-		eecd |= E1000_EECD_CS;
-		E1000_WRITE_REG(hw, EECD, eecd);
-		E1000_WRITE_FLUSH(hw);
-		udelay(eeprom->delay_usec);
-		eecd &= ~E1000_EECD_CS;
-		E1000_WRITE_REG(hw, EECD, eecd);
-		E1000_WRITE_FLUSH(hw);
-		udelay(eeprom->delay_usec);
-	}
-}
-
-/******************************************************************************
- * Terminates a command by inverting the EEPROM's chip select pin
- *
- * hw - Struct containing variables accessed by shared code
- *****************************************************************************/
-static void
-e1000_release_eeprom(struct e1000_hw *hw)
-{
-	uint32_t eecd;
-
-	eecd = E1000_READ_REG(hw, EECD);
-
-	if (hw->eeprom.type == e1000_eeprom_spi) {
-		eecd |= E1000_EECD_CS;  /* Pull CS high */
-		eecd &= ~E1000_EECD_SK; /* Lower SCK */
-
-		E1000_WRITE_REG(hw, EECD, eecd);
-
-		udelay(hw->eeprom.delay_usec);
-	} else if(hw->eeprom.type == e1000_eeprom_microwire) {
-		/* cleanup eeprom */
-
-		/* CS on Microwire is active-high */
-		eecd &= ~(E1000_EECD_CS | E1000_EECD_DI);
-
-		E1000_WRITE_REG(hw, EECD, eecd);
-
-		/* Rising edge of clock */
-		eecd |= E1000_EECD_SK;
-		E1000_WRITE_REG(hw, EECD, eecd);
-		E1000_WRITE_FLUSH(hw);
-		udelay(hw->eeprom.delay_usec);
-
-		/* Falling edge of clock */
-		eecd &= ~E1000_EECD_SK;
-		E1000_WRITE_REG(hw, EECD, eecd);
-		E1000_WRITE_FLUSH(hw);
-		udelay(hw->eeprom.delay_usec);
-	}
-
-	/* Stop requesting EEPROM access */
-	if(hw->mac_type > e1000_82544) {
-		eecd &= ~E1000_EECD_REQ;
-		E1000_WRITE_REG(hw, EECD, eecd);
-	}
-}
-
-/******************************************************************************
- * Reads a 16 bit word from the EEPROM.
- *
- * hw - Struct containing variables accessed by shared code
- *****************************************************************************/
-static int32_t
-e1000_spi_eeprom_ready(struct e1000_hw *hw)
-{
-	uint16_t retry_count = 0;
-	uint8_t spi_stat_reg;
-
-	/* Read "Status Register" repeatedly until the LSB is cleared.  The
-	 * EEPROM will signal that the command has been completed by clearing
-	 * bit 0 of the internal status register.  If it's not cleared within
-	 * 5 milliseconds, then error out.
-	 */
-	retry_count = 0;
-	do {
-		e1000_shift_out_ee_bits(hw, EEPROM_RDSR_OPCODE_SPI,
-		hw->eeprom.opcode_bits);
-		spi_stat_reg = (uint8_t)e1000_shift_in_ee_bits(hw, 8);
-		if (!(spi_stat_reg & EEPROM_STATUS_RDY_SPI))
-			break;
-
-		udelay(5);
-		retry_count += 5;
-
-	} while(retry_count < EEPROM_MAX_RETRY_SPI);
-
-	/* ATMEL SPI write time could vary from 0-20mSec on 3.3V devices (and
-	 * only 0-5mSec on 5V devices)
-	 */
-	if(retry_count >= EEPROM_MAX_RETRY_SPI) {
-		DEBUGOUT("SPI EEPROM Status error\n");
-		return -E1000_ERR_EEPROM;
-	}
-
-	return E1000_SUCCESS;
-}
 
 /******************************************************************************
- * Reads a 16 bit word from the EEPROM.
- *
- * hw - Struct containing variables accessed by shared code
- * offset - offset of  word in the EEPROM to read
- * data - word read from the EEPROM
- * words - number of words to read
- *****************************************************************************/
-static int
-e1000_read_eeprom(struct e1000_hw *hw,
-                  uint16_t offset,
-		  uint16_t words,
-                  uint16_t *data)
-{
-	struct e1000_eeprom_info *eeprom = &hw->eeprom;
-	uint32_t i = 0;
-	
-	DEBUGFUNC("e1000_read_eeprom");
-
-	/* A check for invalid values:  offset too large, too many words, and not
-	 * enough words.
-	 */
-	if((offset > eeprom->word_size) || (words > eeprom->word_size - offset) ||
-	   (words == 0)) {
-		DEBUGOUT("\"words\" parameter out of bounds\n");
-		return -E1000_ERR_EEPROM;
-	}
-
-	/*  Prepare the EEPROM for reading  */
-	if(e1000_acquire_eeprom(hw) != E1000_SUCCESS)
-		return -E1000_ERR_EEPROM;
-
-	if(eeprom->type == e1000_eeprom_spi) {
-		uint16_t word_in;
-		uint8_t read_opcode = EEPROM_READ_OPCODE_SPI;
-
-		if(e1000_spi_eeprom_ready(hw)) {
-			e1000_release_eeprom(hw);
-			return -E1000_ERR_EEPROM;
-		}
-
-		e1000_standby_eeprom(hw);
-
-		/* Some SPI eeproms use the 8th address bit embedded in the opcode */
-		if((eeprom->address_bits == 8) && (offset >= 128))
-			read_opcode |= EEPROM_A8_OPCODE_SPI;
-
-		/* Send the READ command (opcode + addr)  */
-		e1000_shift_out_ee_bits(hw, read_opcode, eeprom->opcode_bits);
-		e1000_shift_out_ee_bits(hw, (uint16_t)(offset*2), eeprom->address_bits);
-
-		/* Read the data.  The address of the eeprom internally increments with
-		 * each byte (spi) being read, saving on the overhead of eeprom setup
-		 * and tear-down.  The address counter will roll over if reading beyond
-		 * the size of the eeprom, thus allowing the entire memory to be read
-		 * starting from any offset. */
-		for (i = 0; i < words; i++) {
-			word_in = e1000_shift_in_ee_bits(hw, 16);
-			data[i] = (word_in >> 8) | (word_in << 8);
-		}
-	} else if(eeprom->type == e1000_eeprom_microwire) {
-		for (i = 0; i < words; i++) {
-			/*  Send the READ command (opcode + addr)  */
-			e1000_shift_out_ee_bits(hw, EEPROM_READ_OPCODE_MICROWIRE,
-						eeprom->opcode_bits);
-			e1000_shift_out_ee_bits(hw, (uint16_t)(offset + i),
-			                        eeprom->address_bits);
-
-			/* Read the data.  For microwire, each word requires the overhead
-			 * of eeprom setup and tear-down. */
-			data[i] = e1000_shift_in_ee_bits(hw, 16);
-			e1000_standby_eeprom(hw);
-		}
-	}
-
-	/* End this read operation */
-	e1000_release_eeprom(hw);
-
-	return E1000_SUCCESS;
-}
-
-/******************************************************************************
- * Verifies that the EEPROM has a valid checksum
- * 
- * hw - Struct containing variables accessed by shared code
- *
- * Reads the first 64 16 bit words of the EEPROM and sums the values read.
- * If the the sum of the 64 16 bit words is 0xBABA, the EEPROM's checksum is
- * valid.
- *****************************************************************************/
-static int
-e1000_validate_eeprom_checksum(struct e1000_hw *hw)
-{
-	uint16_t checksum = 0;
-	uint16_t i, eeprom_data;
-
-	DEBUGFUNC("e1000_validate_eeprom_checksum");
-
-	for(i = 0; i < (EEPROM_CHECKSUM_REG + 1); i++) {
-		if(e1000_read_eeprom(hw, i, 1, &eeprom_data) < 0) {
-			DEBUGOUT("EEPROM Read Error\n");
-			return -E1000_ERR_EEPROM;
-		}
-		checksum += eeprom_data;
-	}
-	
-	if(checksum == (uint16_t) EEPROM_SUM)
-		return E1000_SUCCESS;
-	else {
-		DEBUGOUT("EEPROM Checksum Invalid\n");    
-		return -E1000_ERR_EEPROM;
-	}
-}
-
-/******************************************************************************
- * Reads the adapter's MAC address from the EEPROM and inverts the LSB for the
- * second function of dual function devices
- *
- * hw - Struct containing variables accessed by shared code
- *****************************************************************************/
-static int 
-e1000_read_mac_addr(struct e1000_hw *hw)
-{
-	uint16_t offset;
-	uint16_t eeprom_data;
-	int i;
-
-	DEBUGFUNC("e1000_read_mac_addr");
-
-	for(i = 0; i < NODE_ADDRESS_SIZE; i += 2) {
-		offset = i >> 1;
-		if(e1000_read_eeprom(hw, offset, 1, &eeprom_data) < 0) {
-			DEBUGOUT("EEPROM Read Error\n");
-			return -E1000_ERR_EEPROM;
-		}
-		hw->mac_addr[i] = eeprom_data & 0xff;
-		hw->mac_addr[i+1] = (eeprom_data >> 8) & 0xff;
-	}
-	if(((hw->mac_type == e1000_82546) || (hw->mac_type == e1000_82546_rev_3)) &&
-		(E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1))
-		/* Invert the last bit if this is the second device */
-		hw->mac_addr[5] ^= 1;
-	return E1000_SUCCESS;
-}
-
-/******************************************************************************
- * Initializes receive address filters.
- *
- * hw - Struct containing variables accessed by shared code 
- *
- * Places the MAC address in receive address register 0 and clears the rest
- * of the receive addresss registers. Clears the multicast table. Assumes
- * the receiver is in reset when the routine is called.
- *****************************************************************************/
-static void
-e1000_init_rx_addrs(struct e1000_hw *hw)
-{
-	uint32_t i;
-	uint32_t addr_low;
-	uint32_t addr_high;
-	
-	DEBUGFUNC("e1000_init_rx_addrs");
-	
-	/* Setup the receive address. */
-	DEBUGOUT("Programming MAC Address into RAR[0]\n");
-	addr_low = (hw->mac_addr[0] |
-		(hw->mac_addr[1] << 8) |
-		(hw->mac_addr[2] << 16) | (hw->mac_addr[3] << 24));
-	
-	addr_high = (hw->mac_addr[4] |
-		(hw->mac_addr[5] << 8) | E1000_RAH_AV);
-	
-	E1000_WRITE_REG_ARRAY(hw, RA, 0, addr_low);
-	E1000_WRITE_REG_ARRAY(hw, RA, 1, addr_high);
-	
-	/* Zero out the other 15 receive addresses. */
-	DEBUGOUT("Clearing RAR[1-15]\n");
-	for(i = 1; i < E1000_RAR_ENTRIES; i++) {
-		E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
-		E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
-	}
-}
-
-/******************************************************************************
- * Clears the VLAN filer table
- *
- * hw - Struct containing variables accessed by shared code
- *****************************************************************************/
-static void
-e1000_clear_vfta(struct e1000_hw *hw)
-{
-	uint32_t offset;
-    
-	for(offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++)
-		E1000_WRITE_REG_ARRAY(hw, VFTA, offset, 0);
-}
+ * Inline functions from e1000_hw.c of the linux driver
+ ******************************************************************************/
 
 /******************************************************************************
 * Writes a value to one of the devices registers using port I/O (as opposed to
@@ -733,6 +226,11 @@ static inline void e1000_write_reg_io(struct e1000_hw *hw, uint32_t offset,
 	e1000_io_write(hw, hw->io_base + 4, value);
 }
 
+
+/******************************************************************************
+ * Functions from e1000_hw.c of the linux driver
+ ******************************************************************************/
+
 /******************************************************************************
  * Set the phy type member in the hw struct.
  *
@@ -3252,6 +2750,535 @@ e1000_init_eeprom_params(struct e1000_hw *hw)
 	}
 }
 
+/******************************************************************************
+ * Raises the EEPROM's clock input.
+ *
+ * hw - Struct containing variables accessed by shared code
+ * eecd - EECD's current value
+ *****************************************************************************/
+static void
+e1000_raise_ee_clk(struct e1000_hw *hw,
+                   uint32_t *eecd)
+{
+	/* Raise the clock input to the EEPROM (by setting the SK bit), and then
+	 * wait <delay> microseconds.
+	 */
+	*eecd = *eecd | E1000_EECD_SK;
+	E1000_WRITE_REG(hw, EECD, *eecd);
+	E1000_WRITE_FLUSH(hw);
+	udelay(hw->eeprom.delay_usec);
+}
+
+/******************************************************************************
+ * Lowers the EEPROM's clock input.
+ *
+ * hw - Struct containing variables accessed by shared code 
+ * eecd - EECD's current value
+ *****************************************************************************/
+static void
+e1000_lower_ee_clk(struct e1000_hw *hw,
+                   uint32_t *eecd)
+{
+	/* Lower the clock input to the EEPROM (by clearing the SK bit), and then 
+	 * wait 50 microseconds. 
+	 */
+	*eecd = *eecd & ~E1000_EECD_SK;
+	E1000_WRITE_REG(hw, EECD, *eecd);
+	E1000_WRITE_FLUSH(hw);
+	udelay(hw->eeprom.delay_usec);
+}
+
+/******************************************************************************
+ * Shift data bits out to the EEPROM.
+ *
+ * hw - Struct containing variables accessed by shared code
+ * data - data to send to the EEPROM
+ * count - number of bits to shift out
+ *****************************************************************************/
+static void
+e1000_shift_out_ee_bits(struct e1000_hw *hw,
+                        uint16_t data,
+                        uint16_t count)
+{
+	struct e1000_eeprom_info *eeprom = &hw->eeprom;
+	uint32_t eecd;
+	uint32_t mask;
+	
+	/* We need to shift "count" bits out to the EEPROM. So, value in the
+	 * "data" parameter will be shifted out to the EEPROM one bit at a time.
+	 * In order to do this, "data" must be broken down into bits. 
+	 */
+	mask = 0x01 << (count - 1);
+	eecd = E1000_READ_REG(hw, EECD);
+	if (eeprom->type == e1000_eeprom_microwire) {
+		eecd &= ~E1000_EECD_DO;
+	} else if (eeprom->type == e1000_eeprom_spi) {
+		eecd |= E1000_EECD_DO;
+	}
+	do {
+		/* A "1" is shifted out to the EEPROM by setting bit "DI" to a "1",
+		 * and then raising and then lowering the clock (the SK bit controls
+		 * the clock input to the EEPROM).  A "0" is shifted out to the EEPROM
+		 * by setting "DI" to "0" and then raising and then lowering the clock.
+		 */
+		eecd &= ~E1000_EECD_DI;
+		
+		if(data & mask)
+			eecd |= E1000_EECD_DI;
+		
+		E1000_WRITE_REG(hw, EECD, eecd);
+		E1000_WRITE_FLUSH(hw);
+		
+		udelay(eeprom->delay_usec);
+		
+		e1000_raise_ee_clk(hw, &eecd);
+		e1000_lower_ee_clk(hw, &eecd);
+		
+		mask = mask >> 1;
+		
+	} while(mask);
+
+	/* We leave the "DI" bit set to "0" when we leave this routine. */
+	eecd &= ~E1000_EECD_DI;
+	E1000_WRITE_REG(hw, EECD, eecd);
+}
+
+/******************************************************************************
+ * Shift data bits in from the EEPROM
+ *
+ * hw - Struct containing variables accessed by shared code
+ *****************************************************************************/
+static uint16_t
+e1000_shift_in_ee_bits(struct e1000_hw *hw,
+                       uint16_t count)
+{
+	uint32_t eecd;
+	uint32_t i;
+	uint16_t data;
+	
+	/* In order to read a register from the EEPROM, we need to shift 'count' 
+	 * bits in from the EEPROM. Bits are "shifted in" by raising the clock
+	 * input to the EEPROM (setting the SK bit), and then reading the value of
+	 * the "DO" bit.  During this "shifting in" process the "DI" bit should
+	 * always be clear.
+	 */
+	
+	eecd = E1000_READ_REG(hw, EECD);
+	
+	eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
+	data = 0;
+	
+	for(i = 0; i < count; i++) {
+		data = data << 1;
+		e1000_raise_ee_clk(hw, &eecd);
+		
+		eecd = E1000_READ_REG(hw, EECD);
+		
+		eecd &= ~(E1000_EECD_DI);
+		if(eecd & E1000_EECD_DO)
+			data |= 1;
+		
+		e1000_lower_ee_clk(hw, &eecd);
+	}
+	
+	return data;
+}
+
+/******************************************************************************
+ * Prepares EEPROM for access
+ *
+ * hw - Struct containing variables accessed by shared code
+ *
+ * Lowers EEPROM clock. Clears input pin. Sets the chip select pin. This 
+ * function should be called before issuing a command to the EEPROM.
+ *****************************************************************************/
+static int32_t
+e1000_acquire_eeprom(struct e1000_hw *hw)
+{
+	struct e1000_eeprom_info *eeprom = &hw->eeprom;
+	uint32_t eecd, i=0;
+
+	eecd = E1000_READ_REG(hw, EECD);
+
+	/* Request EEPROM Access */
+	if(hw->mac_type > e1000_82544) {
+		eecd |= E1000_EECD_REQ;
+		E1000_WRITE_REG(hw, EECD, eecd);
+		eecd = E1000_READ_REG(hw, EECD);
+		while((!(eecd & E1000_EECD_GNT)) &&
+		      (i < E1000_EEPROM_GRANT_ATTEMPTS)) {
+			i++;
+			udelay(5);
+			eecd = E1000_READ_REG(hw, EECD);
+		}
+		if(!(eecd & E1000_EECD_GNT)) {
+			eecd &= ~E1000_EECD_REQ;
+			E1000_WRITE_REG(hw, EECD, eecd);
+			DEBUGOUT("Could not acquire EEPROM grant\n");
+			return -E1000_ERR_EEPROM;
+		}
+	}
+
+	/* Setup EEPROM for Read/Write */
+
+	if (eeprom->type == e1000_eeprom_microwire) {
+		/* Clear SK and DI */
+		eecd &= ~(E1000_EECD_DI | E1000_EECD_SK);
+		E1000_WRITE_REG(hw, EECD, eecd);
+
+		/* Set CS */
+		eecd |= E1000_EECD_CS;
+		E1000_WRITE_REG(hw, EECD, eecd);
+	} else if (eeprom->type == e1000_eeprom_spi) {
+		/* Clear SK and CS */
+		eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
+		E1000_WRITE_REG(hw, EECD, eecd);
+		udelay(1);
+	}
+
+	return E1000_SUCCESS;
+}
+
+/******************************************************************************
+ * Returns EEPROM to a "standby" state
+ * 
+ * hw - Struct containing variables accessed by shared code
+ *****************************************************************************/
+static void
+e1000_standby_eeprom(struct e1000_hw *hw)
+{
+	struct e1000_eeprom_info *eeprom = &hw->eeprom;
+	uint32_t eecd;
+	
+	eecd = E1000_READ_REG(hw, EECD);
+
+	if(eeprom->type == e1000_eeprom_microwire) {
+
+		/* Deselect EEPROM */
+		eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
+		E1000_WRITE_REG(hw, EECD, eecd);
+		E1000_WRITE_FLUSH(hw);
+		udelay(eeprom->delay_usec);
+	
+		/* Clock high */
+		eecd |= E1000_EECD_SK;
+		E1000_WRITE_REG(hw, EECD, eecd);
+		E1000_WRITE_FLUSH(hw);
+		udelay(eeprom->delay_usec);
+	
+		/* Select EEPROM */
+		eecd |= E1000_EECD_CS;
+		E1000_WRITE_REG(hw, EECD, eecd);
+		E1000_WRITE_FLUSH(hw);
+		udelay(eeprom->delay_usec);
+
+		/* Clock low */
+		eecd &= ~E1000_EECD_SK;
+		E1000_WRITE_REG(hw, EECD, eecd);
+		E1000_WRITE_FLUSH(hw);
+		udelay(eeprom->delay_usec);
+	} else if(eeprom->type == e1000_eeprom_spi) {
+		/* Toggle CS to flush commands */
+		eecd |= E1000_EECD_CS;
+		E1000_WRITE_REG(hw, EECD, eecd);
+		E1000_WRITE_FLUSH(hw);
+		udelay(eeprom->delay_usec);
+		eecd &= ~E1000_EECD_CS;
+		E1000_WRITE_REG(hw, EECD, eecd);
+		E1000_WRITE_FLUSH(hw);
+		udelay(eeprom->delay_usec);
+	}
+}
+
+/******************************************************************************
+ * Terminates a command by inverting the EEPROM's chip select pin
+ *
+ * hw - Struct containing variables accessed by shared code
+ *****************************************************************************/
+static void
+e1000_release_eeprom(struct e1000_hw *hw)
+{
+	uint32_t eecd;
+
+	eecd = E1000_READ_REG(hw, EECD);
+
+	if (hw->eeprom.type == e1000_eeprom_spi) {
+		eecd |= E1000_EECD_CS;  /* Pull CS high */
+		eecd &= ~E1000_EECD_SK; /* Lower SCK */
+
+		E1000_WRITE_REG(hw, EECD, eecd);
+
+		udelay(hw->eeprom.delay_usec);
+	} else if(hw->eeprom.type == e1000_eeprom_microwire) {
+		/* cleanup eeprom */
+
+		/* CS on Microwire is active-high */
+		eecd &= ~(E1000_EECD_CS | E1000_EECD_DI);
+
+		E1000_WRITE_REG(hw, EECD, eecd);
+
+		/* Rising edge of clock */
+		eecd |= E1000_EECD_SK;
+		E1000_WRITE_REG(hw, EECD, eecd);
+		E1000_WRITE_FLUSH(hw);
+		udelay(hw->eeprom.delay_usec);
+
+		/* Falling edge of clock */
+		eecd &= ~E1000_EECD_SK;
+		E1000_WRITE_REG(hw, EECD, eecd);
+		E1000_WRITE_FLUSH(hw);
+		udelay(hw->eeprom.delay_usec);
+	}
+
+	/* Stop requesting EEPROM access */
+	if(hw->mac_type > e1000_82544) {
+		eecd &= ~E1000_EECD_REQ;
+		E1000_WRITE_REG(hw, EECD, eecd);
+	}
+}
+
+/******************************************************************************
+ * Reads a 16 bit word from the EEPROM.
+ *
+ * hw - Struct containing variables accessed by shared code
+ *****************************************************************************/
+static int32_t
+e1000_spi_eeprom_ready(struct e1000_hw *hw)
+{
+	uint16_t retry_count = 0;
+	uint8_t spi_stat_reg;
+
+	/* Read "Status Register" repeatedly until the LSB is cleared.  The
+	 * EEPROM will signal that the command has been completed by clearing
+	 * bit 0 of the internal status register.  If it's not cleared within
+	 * 5 milliseconds, then error out.
+	 */
+	retry_count = 0;
+	do {
+		e1000_shift_out_ee_bits(hw, EEPROM_RDSR_OPCODE_SPI,
+		hw->eeprom.opcode_bits);
+		spi_stat_reg = (uint8_t)e1000_shift_in_ee_bits(hw, 8);
+		if (!(spi_stat_reg & EEPROM_STATUS_RDY_SPI))
+			break;
+
+		udelay(5);
+		retry_count += 5;
+
+	} while(retry_count < EEPROM_MAX_RETRY_SPI);
+
+	/* ATMEL SPI write time could vary from 0-20mSec on 3.3V devices (and
+	 * only 0-5mSec on 5V devices)
+	 */
+	if(retry_count >= EEPROM_MAX_RETRY_SPI) {
+		DEBUGOUT("SPI EEPROM Status error\n");
+		return -E1000_ERR_EEPROM;
+	}
+
+	return E1000_SUCCESS;
+}
+
+/******************************************************************************
+ * Reads a 16 bit word from the EEPROM.
+ *
+ * hw - Struct containing variables accessed by shared code
+ * offset - offset of  word in the EEPROM to read
+ * data - word read from the EEPROM
+ * words - number of words to read
+ *****************************************************************************/
+static int
+e1000_read_eeprom(struct e1000_hw *hw,
+                  uint16_t offset,
+		  uint16_t words,
+                  uint16_t *data)
+{
+	struct e1000_eeprom_info *eeprom = &hw->eeprom;
+	uint32_t i = 0;
+	
+	DEBUGFUNC("e1000_read_eeprom");
+
+	/* A check for invalid values:  offset too large, too many words, and not
+	 * enough words.
+	 */
+	if((offset > eeprom->word_size) || (words > eeprom->word_size - offset) ||
+	   (words == 0)) {
+		DEBUGOUT("\"words\" parameter out of bounds\n");
+		return -E1000_ERR_EEPROM;
+	}
+
+	/*  Prepare the EEPROM for reading  */
+	if(e1000_acquire_eeprom(hw) != E1000_SUCCESS)
+		return -E1000_ERR_EEPROM;
+
+	if(eeprom->type == e1000_eeprom_spi) {
+		uint16_t word_in;
+		uint8_t read_opcode = EEPROM_READ_OPCODE_SPI;
+
+		if(e1000_spi_eeprom_ready(hw)) {
+			e1000_release_eeprom(hw);
+			return -E1000_ERR_EEPROM;
+		}
+
+		e1000_standby_eeprom(hw);
+
+		/* Some SPI eeproms use the 8th address bit embedded in the opcode */
+		if((eeprom->address_bits == 8) && (offset >= 128))
+			read_opcode |= EEPROM_A8_OPCODE_SPI;
+
+		/* Send the READ command (opcode + addr)  */
+		e1000_shift_out_ee_bits(hw, read_opcode, eeprom->opcode_bits);
+		e1000_shift_out_ee_bits(hw, (uint16_t)(offset*2), eeprom->address_bits);
+
+		/* Read the data.  The address of the eeprom internally increments with
+		 * each byte (spi) being read, saving on the overhead of eeprom setup
+		 * and tear-down.  The address counter will roll over if reading beyond
+		 * the size of the eeprom, thus allowing the entire memory to be read
+		 * starting from any offset. */
+		for (i = 0; i < words; i++) {
+			word_in = e1000_shift_in_ee_bits(hw, 16);
+			data[i] = (word_in >> 8) | (word_in << 8);
+		}
+	} else if(eeprom->type == e1000_eeprom_microwire) {
+		for (i = 0; i < words; i++) {
+			/*  Send the READ command (opcode + addr)  */
+			e1000_shift_out_ee_bits(hw, EEPROM_READ_OPCODE_MICROWIRE,
+						eeprom->opcode_bits);
+			e1000_shift_out_ee_bits(hw, (uint16_t)(offset + i),
+			                        eeprom->address_bits);
+
+			/* Read the data.  For microwire, each word requires the overhead
+			 * of eeprom setup and tear-down. */
+			data[i] = e1000_shift_in_ee_bits(hw, 16);
+			e1000_standby_eeprom(hw);
+		}
+	}
+
+	/* End this read operation */
+	e1000_release_eeprom(hw);
+
+	return E1000_SUCCESS;
+}
+
+/******************************************************************************
+ * Verifies that the EEPROM has a valid checksum
+ * 
+ * hw - Struct containing variables accessed by shared code
+ *
+ * Reads the first 64 16 bit words of the EEPROM and sums the values read.
+ * If the the sum of the 64 16 bit words is 0xBABA, the EEPROM's checksum is
+ * valid.
+ *****************************************************************************/
+static int
+e1000_validate_eeprom_checksum(struct e1000_hw *hw)
+{
+	uint16_t checksum = 0;
+	uint16_t i, eeprom_data;
+
+	DEBUGFUNC("e1000_validate_eeprom_checksum");
+
+	for(i = 0; i < (EEPROM_CHECKSUM_REG + 1); i++) {
+		if(e1000_read_eeprom(hw, i, 1, &eeprom_data) < 0) {
+			DEBUGOUT("EEPROM Read Error\n");
+			return -E1000_ERR_EEPROM;
+		}
+		checksum += eeprom_data;
+	}
+	
+	if(checksum == (uint16_t) EEPROM_SUM)
+		return E1000_SUCCESS;
+	else {
+		DEBUGOUT("EEPROM Checksum Invalid\n");    
+		return -E1000_ERR_EEPROM;
+	}
+}
+
+/******************************************************************************
+ * Reads the adapter's MAC address from the EEPROM and inverts the LSB for the
+ * second function of dual function devices
+ *
+ * hw - Struct containing variables accessed by shared code
+ *****************************************************************************/
+static int 
+e1000_read_mac_addr(struct e1000_hw *hw)
+{
+	uint16_t offset;
+	uint16_t eeprom_data;
+	int i;
+
+	DEBUGFUNC("e1000_read_mac_addr");
+
+	for(i = 0; i < NODE_ADDRESS_SIZE; i += 2) {
+		offset = i >> 1;
+		if(e1000_read_eeprom(hw, offset, 1, &eeprom_data) < 0) {
+			DEBUGOUT("EEPROM Read Error\n");
+			return -E1000_ERR_EEPROM;
+		}
+		hw->mac_addr[i] = eeprom_data & 0xff;
+		hw->mac_addr[i+1] = (eeprom_data >> 8) & 0xff;
+	}
+	if(((hw->mac_type == e1000_82546) || (hw->mac_type == e1000_82546_rev_3)) &&
+		(E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1))
+		/* Invert the last bit if this is the second device */
+		hw->mac_addr[5] ^= 1;
+	return E1000_SUCCESS;
+}
+
+/******************************************************************************
+ * Initializes receive address filters.
+ *
+ * hw - Struct containing variables accessed by shared code 
+ *
+ * Places the MAC address in receive address register 0 and clears the rest
+ * of the receive addresss registers. Clears the multicast table. Assumes
+ * the receiver is in reset when the routine is called.
+ *****************************************************************************/
+static void
+e1000_init_rx_addrs(struct e1000_hw *hw)
+{
+	uint32_t i;
+	uint32_t addr_low;
+	uint32_t addr_high;
+	
+	DEBUGFUNC("e1000_init_rx_addrs");
+	
+	/* Setup the receive address. */
+	DEBUGOUT("Programming MAC Address into RAR[0]\n");
+	addr_low = (hw->mac_addr[0] |
+		(hw->mac_addr[1] << 8) |
+		(hw->mac_addr[2] << 16) | (hw->mac_addr[3] << 24));
+	
+	addr_high = (hw->mac_addr[4] |
+		(hw->mac_addr[5] << 8) | E1000_RAH_AV);
+	
+	E1000_WRITE_REG_ARRAY(hw, RA, 0, addr_low);
+	E1000_WRITE_REG_ARRAY(hw, RA, 1, addr_high);
+	
+	/* Zero out the other 15 receive addresses. */
+	DEBUGOUT("Clearing RAR[1-15]\n");
+	for(i = 1; i < E1000_RAR_ENTRIES; i++) {
+		E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
+		E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
+	}
+}
+
+/******************************************************************************
+ * Clears the VLAN filer table
+ *
+ * hw - Struct containing variables accessed by shared code
+ *****************************************************************************/
+static void
+e1000_clear_vfta(struct e1000_hw *hw)
+{
+	uint32_t offset;
+    
+	for(offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++)
+		E1000_WRITE_REG_ARRAY(hw, VFTA, offset, 0);
+}
+
+
+/******************************************************************************
+ * Functions from e1000_main.c of the linux driver
+ ******************************************************************************/
+
 /**
  * e1000_reset - Reset the adapter
  */
@@ -3357,6 +3384,11 @@ e1000_sw_init(struct pci_device *pdev, struct e1000_hw *hw)
 	return E1000_SUCCESS;
 }
 
+
+/******************************************************************************
+ * Functions not present in the linux driver
+ ******************************************************************************/
+
 static void fill_rx (void)
 {
 	struct e1000_rx_desc *rd;
diff --git a/src/drivers/net/eepro.c b/src/drivers/net/eepro.c
index 6c2318bdd..65c6c8f59 100644
--- a/src/drivers/net/eepro.c
+++ b/src/drivers/net/eepro.c
@@ -19,6 +19,12 @@ has 34 pins, the top row of 2 are not used.
 ***************************************************************************/
 
 /*
+
+ timlegge	2005-05-18	remove the relocation changes cards that 
+				write directly to the hardware don't need it
+*/
+
+/*
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License as
  * published by the Free Software Foundation; either version 2, or (at
@@ -257,8 +263,8 @@ static unsigned eeprom_reg = EEPROM_REG_PRO;
 #define eeprom_delay() { udelay(40); }
 #define EE_READ_CMD (6 << 6)
 
-/* do a full reset */
-#define eepro_full_reset(ioaddr)	outb(RESET_CMD, ioaddr); udelay(40);
+/* do a full reset; data sheet asks for 250us delay */
+#define eepro_full_reset(ioaddr)	outb(RESET_CMD, ioaddr); udelay(255);
 
 /* do a nice reset */
 #define eepro_sel_reset(ioaddr) 	{ \
@@ -320,13 +326,15 @@ static void eepro_reset(struct nic *nic)
 	eepro_sw2bank0(nic->ioaddr);	/* Switch back to bank 0 */
 	eepro_clear_int(nic->ioaddr);
 	/* Initialise RCV */
-	rx_start = (unsigned int)bus_to_virt(RCV_LOWER_LIMIT << 8);
-	outw(RCV_LOWER_LIMIT << 8, nic->ioaddr + RCV_BAR);
+	outw(rx_start = (RCV_LOWER_LIMIT << 8), nic->ioaddr + RCV_BAR);
 	outw(((RCV_UPPER_LIMIT << 8) | 0xFE), nic->ioaddr + RCV_STOP);
+ 	/* Make sure 1st poll won't find a valid packet header */
+ 	outw((RCV_LOWER_LIMIT << 8), nic->ioaddr + HOST_ADDRESS_REG);
+ 	outw(0,                      nic->ioaddr + IO_PORT);
 	/* Intialise XMT */
 	outw((XMT_LOWER_LIMIT << 8), nic->ioaddr + xmt_bar);
 	eepro_sel_reset(nic->ioaddr);
-	tx_start = tx_end = (unsigned int)bus_to_virt(XMT_LOWER_LIMIT << 8);
+	tx_start = tx_end = (XMT_LOWER_LIMIT << 8);
 	tx_last = 0;
 	eepro_en_rx(nic->ioaddr);
 }
@@ -336,7 +344,7 @@ POLL - Wait for a frame
 ***************************************************************************/
 static int eepro_poll(struct nic *nic, int retrieve)
 {
-	unsigned int	rcv_car = virt_to_bus((void *)rx_start);
+	unsigned int	rcv_car = rx_start;
 	unsigned int	rcv_event, rcv_status, rcv_next_frame, rcv_size;
 
 	/* return true if there's an ethernet packet ready to read */
@@ -380,8 +388,12 @@ static int eepro_poll(struct nic *nic, int retrieve)
 }
 #endif
 	nic->packetlen = rcv_size;
-	rcv_car  = virt_to_bus((void *) (rx_start + RCV_HEADER + rcv_size));
-	rx_start = (unsigned int)bus_to_virt(rcv_next_frame << 8);
+	rcv_car  = (rx_start + RCV_HEADER + rcv_size);
+	rx_start = rcv_next_frame;
+/* 
+	hex_dump(rcv_car, nic->packetlen); 
+*/
+
 	if (rcv_car == 0)
 		rcv_car = ((RCV_UPPER_LIMIT << 8) | 0xff);
 	outw(rcv_car - 1, nic->ioaddr + RCV_STOP);
@@ -455,7 +467,7 @@ static void eepro_disable ( struct nic *nic, struct isa_device *isa __unused ) {
 	eepro_sw2bank0(nic->ioaddr);	/* Switch to bank 0 */
 	/* Flush the Tx and disable Rx */
 	outb(STOP_RCV_CMD, nic->ioaddr);
-	tx_start = tx_end = (unsigned int) (bus_to_virt(XMT_LOWER_LIMIT << 8));
+	tx_start = tx_end = (XMT_LOWER_LIMIT << 8);
 	tx_last = 0;
 	/* Reset the 82595 */
 	eepro_full_reset(nic->ioaddr);
diff --git a/src/drivers/net/eepro100.c b/src/drivers/net/eepro100.c
index 590b37c8d..d97b1b187 100644
--- a/src/drivers/net/eepro100.c
+++ b/src/drivers/net/eepro100.c
@@ -110,13 +110,6 @@
 
 static int ioaddr;
 
-typedef unsigned char  u8;
-typedef   signed char  s8;
-typedef unsigned short u16;
-typedef   signed short s16;
-typedef unsigned int   u32;
-typedef   signed int   s32;
-
 enum speedo_offsets {
   SCBStatus = 0, SCBCmd = 2,      /* Rx/Command Unit command and status. */
   SCBPointer = 4,                 /* General purpose pointer. */
diff --git a/src/drivers/net/forcedeth.c b/src/drivers/net/forcedeth.c
index 3297effd1..637738362 100644
--- a/src/drivers/net/forcedeth.c
+++ b/src/drivers/net/forcedeth.c
@@ -30,14 +30,16 @@
 *	(C) 2003 Manfred Spraul
 *		See Linux Driver for full information
 *	
-*	Linux Driver Version 0.22, 19 Jan 2004
+*	Linux Driver Version 0.30, 25 Sep 2004
+*	Linux Kernel 2.6.10
 * 
 * 
 *    REVISION HISTORY:
 *    ================
 *    v1.0	01-31-2004	timlegge	Initial port of Linux driver
 *    v1.1	02-03-2004	timlegge	Large Clean up, first release 
-*    
+*    v1.2	05-14-2005	timlegge	Add Linux 0.22 to .030 features
+*
 *    Indent Options: indent -kr -i8
 ***************************************************************************/
 
@@ -49,9 +51,10 @@
 #include "pci.h"
 /* Include timer support functions */
 #include "timer.h"
+#include "mii.h"
 
-#define drv_version "v1.1"
-#define drv_date "02-03-2004"
+#define drv_version "v1.2"
+#define drv_date "05-14-2005"
 
 //#define TFTM_DEBUG
 #ifdef TFTM_DEBUG
@@ -60,12 +63,7 @@
 #define dprintf(x)
 #endif
 
-typedef unsigned char u8;
-typedef signed char s8;
-typedef unsigned short u16;
-typedef signed short s16;
-typedef unsigned int u32;
-typedef signed int s32;
+#define ETH_DATA_LEN   1500
 
 /* Condensed operations for readability. */
 #define virt_to_le32desc(addr)  cpu_to_le32(virt_to_bus(addr))
@@ -73,22 +71,35 @@ typedef signed int s32;
 
 static unsigned long BASE;
 /* NIC specific static variables go here */
+#define PCI_DEVICE_ID_NVIDIA_NVENET_1           0x01c3
+#define PCI_DEVICE_ID_NVIDIA_NVENET_2           0x0066
+#define PCI_DEVICE_ID_NVIDIA_NVENET_4           0x0086
+#define PCI_DEVICE_ID_NVIDIA_NVENET_5           0x008c
+#define PCI_DEVICE_ID_NVIDIA_NVENET_3           0x00d6
+#define PCI_DEVICE_ID_NVIDIA_NVENET_7           0x00df
+#define PCI_DEVICE_ID_NVIDIA_NVENET_6           0x00e6
+#define PCI_DEVICE_ID_NVIDIA_NVENET_8           0x0056
+#define PCI_DEVICE_ID_NVIDIA_NVENET_9           0x0057
+#define PCI_DEVICE_ID_NVIDIA_NVENET_10          0x0037
+#define PCI_DEVICE_ID_NVIDIA_NVENET_11          0x0038
 
 
 /*
  * Hardware access:
  */
 
-#define DEV_NEED_LASTPACKET1	0x0001
-#define DEV_IRQMASK_1		0x0002
-#define DEV_IRQMASK_2		0x0004
-#define DEV_NEED_TIMERIRQ	0x0008
+#define DEV_NEED_LASTPACKET1	0x0001	/* set LASTPACKET1 in tx flags */
+#define DEV_IRQMASK_1		0x0002	/* use NVREG_IRQMASK_WANTED_1 for irq mask */
+#define DEV_IRQMASK_2		0x0004	/* use NVREG_IRQMASK_WANTED_2 for irq mask */
+#define DEV_NEED_TIMERIRQ	0x0008	/* set the timer irq flag in the irq mask */
+#define DEV_NEED_LINKTIMER	0x0010	/* poll link settings. Relies on the timer irq */
 
 enum {
 	NvRegIrqStatus = 0x000,
 #define NVREG_IRQSTAT_MIIEVENT	0040
 #define NVREG_IRQSTAT_MASK		0x1ff
 	NvRegIrqMask = 0x004,
+#define NVREG_IRQ_RX_ERROR		0x0001
 #define NVREG_IRQ_RX			0x0002
 #define NVREG_IRQ_RX_NOBUF		0x0004
 #define NVREG_IRQ_TX_ERR		0x0008
@@ -98,7 +109,7 @@ enum {
 #define NVREG_IRQ_TX1			0x0100
 #define NVREG_IRQMASK_WANTED_1		0x005f
 #define NVREG_IRQMASK_WANTED_2		0x0147
-#define NVREG_IRQ_UNKNOWN		(~(NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF|NVREG_IRQ_TX_ERR|NVREG_IRQ_TX2|NVREG_IRQ_TIMER|NVREG_IRQ_LINK|NVREG_IRQ_TX1))
+#define NVREG_IRQ_UNKNOWN		(~(NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF|NVREG_IRQ_TX_ERR|NVREG_IRQ_TX2|NVREG_IRQ_TIMER|NVREG_IRQ_LINK|NVREG_IRQ_TX1))
 
 	NvRegUnknownSetupReg6 = 0x008,
 #define NVREG_UNKSETUP6_VAL		3
@@ -125,7 +136,7 @@ enum {
 
 	NvRegOffloadConfig = 0x90,
 #define NVREG_OFFLOAD_HOMEPHY	0x601
-#define NVREG_OFFLOAD_NORMAL	0x5ee
+#define NVREG_OFFLOAD_NORMAL	RX_NIC_BUFSIZE
 	NvRegReceiverControl = 0x094,
 #define NVREG_RCVCTL_START	0x01
 	NvRegReceiverStatus = 0x98,
@@ -134,6 +145,8 @@ enum {
 	NvRegRandomSeed = 0x9c,
 #define NVREG_RNDSEED_MASK	0x00ff
 #define NVREG_RNDSEED_FORCE	0x7f00
+#define NVREG_RNDSEED_FORCE2	0x2d00
+#define NVREG_RNDSEED_FORCE3	0x7400
 
 	NvRegUnknownSetupReg1 = 0xA0,
 #define NVREG_UNKSETUP1_VAL	0x16070f
@@ -147,6 +160,9 @@ enum {
 	NvRegMulticastMaskA = 0xB8,
 	NvRegMulticastMaskB = 0xBC,
 
+	NvRegPhyInterface = 0xC0,
+#define PHY_RGMII		0x10000000
+
 	NvRegTxRingPhysAddr = 0x100,
 	NvRegRxRingPhysAddr = 0x104,
 	NvRegRingSizes = 0x108,
@@ -155,12 +171,12 @@ enum {
 	NvRegUnknownTransmitterReg = 0x10c,
 	NvRegLinkSpeed = 0x110,
 #define NVREG_LINKSPEED_FORCE 0x10000
-#define NVREG_LINKSPEED_10	10
+#define NVREG_LINKSPEED_10	1000
 #define NVREG_LINKSPEED_100	100
-#define NVREG_LINKSPEED_1000	1000
+#define NVREG_LINKSPEED_1000	50
 	NvRegUnknownSetupReg5 = 0x130,
 #define NVREG_UNKSETUP5_BIT31	(1<<31)
-	NvRegUnknownSetupReg3 = 0x134,
+	NvRegUnknownSetupReg3 = 0x13c,
 #define NVREG_UNKSETUP3_VAL1	0x200010
 	NvRegTxRxControl = 0x144,
 #define NVREG_TXRXCTL_KICK	0x0001
@@ -168,6 +184,7 @@ enum {
 #define NVREG_TXRXCTL_BIT2	0x0004
 #define NVREG_TXRXCTL_IDLE	0x0008
 #define NVREG_TXRXCTL_RESET	0x0010
+#define NVREG_TXRXCTL_RXCHECK	0x0400
 	NvRegMIIStatus = 0x180,
 #define NVREG_MIISTAT_ERROR		0x0001
 #define NVREG_MIISTAT_LINKCHANGE	0x0008
@@ -179,15 +196,15 @@ enum {
 	NvRegAdapterControl = 0x188,
 #define NVREG_ADAPTCTL_START	0x02
 #define NVREG_ADAPTCTL_LINKUP	0x04
-#define NVREG_ADAPTCTL_PHYVALID	0x4000
+#define NVREG_ADAPTCTL_PHYVALID	0x40000
 #define NVREG_ADAPTCTL_RUNNING	0x100000
 #define NVREG_ADAPTCTL_PHYSHIFT	24
 	NvRegMIISpeed = 0x18c,
 #define NVREG_MIISPEED_BIT8	(1<<8)
 #define NVREG_MIIDELAY	5
 	NvRegMIIControl = 0x190,
-#define NVREG_MIICTL_INUSE	0x10000
-#define NVREG_MIICTL_WRITE	0x08000
+#define NVREG_MIICTL_INUSE	0x08000
+#define NVREG_MIICTL_WRITE	0x00400
 #define NVREG_MIICTL_ADDRSHIFT	5
 	NvRegMIIData = 0x194,
 	NvRegWakeUpFlags = 0x200,
@@ -201,6 +218,7 @@ enum {
 #define NVREG_WAKEUPFLAGS_ACCEPT_MAGPAT		0x01
 #define NVREG_WAKEUPFLAGS_ACCEPT_WAKEUPPAT	0x02
 #define NVREG_WAKEUPFLAGS_ACCEPT_LINKCHANGE	0x04
+#define NVREG_WAKEUPFLAGS_ENABLE	0x1111
 
 	NvRegPatternCRC = 0x204,
 	NvRegPatternMask = 0x208,
@@ -218,30 +236,61 @@ enum {
 #define NVREG_POWERSTATE_D3		0x0003
 };
 
-
-
-#define NV_TX_LASTPACKET	(1<<0)
-#define NV_TX_RETRYERROR	(1<<3)
-#define NV_TX_LASTPACKET1	(1<<8)
-#define NV_TX_DEFERRED		(1<<10)
-#define NV_TX_CARRIERLOST	(1<<11)
-#define NV_TX_LATECOLLISION	(1<<12)
-#define NV_TX_UNDERFLOW		(1<<13)
-#define NV_TX_ERROR		(1<<14)
-#define NV_TX_VALID		(1<<15)
-
-#define NV_RX_DESCRIPTORVALID	(1<<0)
-#define NV_RX_MISSEDFRAME	(1<<1)
-#define NV_RX_SUBSTRACT1	(1<<3)
-#define NV_RX_ERROR1		(1<<7)
-#define NV_RX_ERROR2		(1<<8)
-#define NV_RX_ERROR3		(1<<9)
-#define NV_RX_ERROR4		(1<<10)
-#define NV_RX_CRCERR		(1<<11)
-#define NV_RX_OVERFLOW		(1<<12)
-#define NV_RX_FRAMINGERR	(1<<13)
-#define NV_RX_ERROR		(1<<14)
-#define NV_RX_AVAIL		(1<<15)
+#define FLAG_MASK_V1 0xffff0000
+#define FLAG_MASK_V2 0xffffc000
+#define LEN_MASK_V1 (0xffffffff ^ FLAG_MASK_V1)
+#define LEN_MASK_V2 (0xffffffff ^ FLAG_MASK_V2)
+
+#define NV_TX_LASTPACKET	(1<<16)
+#define NV_TX_RETRYERROR	(1<<19)
+#define NV_TX_LASTPACKET1	(1<<24)
+#define NV_TX_DEFERRED		(1<<26)
+#define NV_TX_CARRIERLOST	(1<<27)
+#define NV_TX_LATECOLLISION	(1<<28)
+#define NV_TX_UNDERFLOW		(1<<29)
+#define NV_TX_ERROR		(1<<30)
+#define NV_TX_VALID		(1<<31)
+
+#define NV_TX2_LASTPACKET	(1<<29)
+#define NV_TX2_RETRYERROR	(1<<18)
+#define NV_TX2_LASTPACKET1	(1<<23)
+#define NV_TX2_DEFERRED		(1<<25)
+#define NV_TX2_CARRIERLOST	(1<<26)
+#define NV_TX2_LATECOLLISION	(1<<27)
+#define NV_TX2_UNDERFLOW	(1<<28)
+/* error and valid are the same for both */
+#define NV_TX2_ERROR		(1<<30)
+#define NV_TX2_VALID		(1<<31)
+
+#define NV_RX_DESCRIPTORVALID	(1<<16)
+#define NV_RX_MISSEDFRAME	(1<<17)
+#define NV_RX_SUBSTRACT1	(1<<18)
+#define NV_RX_ERROR1		(1<<23)
+#define NV_RX_ERROR2		(1<<24)
+#define NV_RX_ERROR3		(1<<25)
+#define NV_RX_ERROR4		(1<<26)
+#define NV_RX_CRCERR		(1<<27)
+#define NV_RX_OVERFLOW		(1<<28)
+#define NV_RX_FRAMINGERR	(1<<29)
+#define NV_RX_ERROR		(1<<30)
+#define NV_RX_AVAIL		(1<<31)
+
+#define NV_RX2_CHECKSUMMASK	(0x1C000000)
+#define NV_RX2_CHECKSUMOK1	(0x10000000)
+#define NV_RX2_CHECKSUMOK2	(0x14000000)
+#define NV_RX2_CHECKSUMOK3	(0x18000000)
+#define NV_RX2_DESCRIPTORVALID	(1<<29)
+#define NV_RX2_SUBSTRACT1	(1<<25)
+#define NV_RX2_ERROR1		(1<<18)
+#define NV_RX2_ERROR2		(1<<19)
+#define NV_RX2_ERROR3		(1<<20)
+#define NV_RX2_ERROR4		(1<<21)
+#define NV_RX2_CRCERR		(1<<22)
+#define NV_RX2_OVERFLOW		(1<<23)
+#define NV_RX2_FRAMINGERR	(1<<24)
+/* error and avail are the same for both */
+#define NV_RX2_ERROR		(1<<30)
+#define NV_RX2_AVAIL		(1<<31)
 
 /* Miscelaneous hardware related defines: */
 #define NV_PCI_REGSZ		0x270
@@ -266,27 +315,73 @@ enum {
 #define NV_WAKEUPMASKENTRIES	4
 
 /* General driver defaults */
-#define NV_WATCHDOG_TIMEO	(2*HZ)
-#define DEFAULT_MTU		1500	/* also maximum supported, at least for now */
+#define NV_WATCHDOG_TIMEO	(5*HZ)
 
 #define RX_RING		4
 #define TX_RING		2
-/* limited to 1 packet until we understand NV_TX_LASTPACKET */
-#define TX_LIMIT_STOP	10
-#define TX_LIMIT_START	5
+
+/* 
+ * If your nic mysteriously hangs then try to reduce the limits
+ * to 1/0: It might be required to set NV_TX_LASTPACKET in the
+ * last valid ring entry. But this would be impossible to
+ * implement - probably a disassembly error.
+ */
+#define TX_LIMIT_STOP	63
+#define TX_LIMIT_START	62
 
 /* rx/tx mac addr + type + vlan + align + slack*/
-#define RX_NIC_BUFSIZE		(DEFAULT_MTU + 64)
+#define RX_NIC_BUFSIZE		(ETH_DATA_LEN + 64)
 /* even more slack */
-#define RX_ALLOC_BUFSIZE	(DEFAULT_MTU + 128)
+#define RX_ALLOC_BUFSIZE	(ETH_DATA_LEN + 128)
 
 #define OOM_REFILL	(1+HZ/20)
 #define POLL_WAIT	(1+HZ/100)
-
+#define LINK_TIMEOUT	(3*HZ)
+
+/* 
+ * desc_ver values:
+ * This field has two purposes:
+ * - Newer nics uses a different ring layout. The layout is selected by
+ *   comparing np->desc_ver with DESC_VER_xy.
+ * - It contains bits that are forced on when writing to NvRegTxRxControl.
+ */
+#define DESC_VER_1	0x0
+#define DESC_VER_2	(0x02100|NVREG_TXRXCTL_RXCHECK)
+
+/* PHY defines */
+#define PHY_OUI_MARVELL	0x5043
+#define PHY_OUI_CICADA	0x03f1
+#define PHYID1_OUI_MASK	0x03ff
+#define PHYID1_OUI_SHFT	6
+#define PHYID2_OUI_MASK	0xfc00
+#define PHYID2_OUI_SHFT	10
+#define PHY_INIT1	0x0f000
+#define PHY_INIT2	0x0e00
+#define PHY_INIT3	0x01000
+#define PHY_INIT4	0x0200
+#define PHY_INIT5	0x0004
+#define PHY_INIT6	0x02000
+#define PHY_GIGABIT	0x0100
+
+#define PHY_TIMEOUT	0x1
+#define PHY_ERROR	0x2
+
+#define PHY_100	0x1
+#define PHY_1000	0x2
+#define PHY_HALF	0x100
+
+/* FIXME: MII defines that should be added to <linux/mii.h> */
+#define MII_1000BT_CR	0x09
+#define MII_1000BT_SR	0x0a
+#define ADVERTISE_1000FULL	0x0200
+#define ADVERTISE_1000HALF	0x0100
+#define LPA_1000FULL	0x0800
+#define LPA_1000HALF	0x0400
+
+/* Big endian: should work, but is untested */
 struct ring_desc {
 	u32 PacketBuffer;
-	u16 Length;
-	u16 Flags;
+	u32 FlagLen;
 };
 
 
@@ -310,22 +405,25 @@ static struct forcedeth_private {
 	u32 linkspeed;
 	int duplex;
 	int phyaddr;
+	int wolenabled;
+	unsigned int phy_oui;
+	u16 gigabit;
 
 	/* General data: RO fields */
 	u8 *ring_addr;
 	u32 orig_mac[2];
 	u32 irqmask;
+	u32 desc_ver;
 	/* rx specific fields.
 	 * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
 	 */
 	unsigned int cur_rx, refill_rx;
-	unsigned int rx_buf_sz;
 
 	/*
 	 * tx specific fields.
 	 */
 	unsigned int next_tx, nic_tx;
-	u16 tx_flags;
+	u32 tx_flags;
 } npx;
 
 static struct forcedeth_private *np;
@@ -335,6 +433,13 @@ static inline void pci_push(u8 * base)
 	/* force out pending posted writes */
 	readl(base);
 }
+
+static inline u32 nv_descr_getlength(struct ring_desc *prd, u32 v)
+{
+	return le32_to_cpu(prd->FlagLen)
+	    & ((v == DESC_VER_1) ? LEN_MASK_V1 : LEN_MASK_V2);
+}
+
 static int reg_delay(int offset, u32 mask,
 		     u32 target, int delay, int delaymax, const char *msg)
 {
@@ -383,18 +488,11 @@ static int mii_rw(struct nic *nic __unused, int addr, int miireg,
 		  int value)
 {
 	u8 *base = (u8 *) BASE;
-	int was_running;
 	u32 reg;
 	int retval;
 
 	writel(NVREG_MIISTAT_MASK, base + NvRegMIIStatus);
-	was_running = 0;
-	reg = readl(base + NvRegAdapterControl);
-	if (reg & NVREG_ADAPTCTL_RUNNING) {
-		was_running = 1;
-		writel(reg & ~NVREG_ADAPTCTL_RUNNING,
-		       base + NvRegAdapterControl);
-	}
+
 	reg = readl(base + NvRegMIIControl);
 	if (reg & NVREG_MIICTL_INUSE) {
 		writel(NVREG_MIICTL_INUSE, base + NvRegMIIControl);
@@ -402,7 +500,7 @@ static int mii_rw(struct nic *nic __unused, int addr, int miireg,
 	}
 
 	reg =
-	    NVREG_MIICTL_INUSE | (addr << NVREG_MIICTL_ADDRSHIFT) | miireg;
+	    (addr << NVREG_MIICTL_ADDRSHIFT) | miireg;
 	if (value != MII_READ) {
 		writel(value, base + NvRegMIIData);
 		reg |= NVREG_MIICTL_WRITE;
@@ -424,20 +522,123 @@ static int mii_rw(struct nic *nic __unused, int addr, int miireg,
 			 miireg, addr));
 		retval = -1;
 	} else {
-		/* FIXME: why is that required? */
-		udelay(50);
 		retval = readl(base + NvRegMIIData);
 		dprintf(("mii_rw read from reg %d at PHY %d: 0x%x.\n",
 			 miireg, addr, retval));
 	}
-	if (was_running) {
-		reg = readl(base + NvRegAdapterControl);
-		writel(reg | NVREG_ADAPTCTL_RUNNING,
-		       base + NvRegAdapterControl);
-	}
 	return retval;
 }
 
+static int phy_reset(struct nic *nic)
+{
+
+	u32 miicontrol;
+	unsigned int tries = 0;
+
+	miicontrol = mii_rw(nic, np->phyaddr, MII_BMCR, MII_READ);
+	miicontrol |= BMCR_RESET;
+	if (mii_rw(nic, np->phyaddr, MII_BMCR, miicontrol)) {
+		return -1;
+	}
+
+	/* wait for 500ms */
+	mdelay(500);
+
+	/* must wait till reset is deasserted */
+	while (miicontrol & BMCR_RESET) {
+		mdelay(10);
+		miicontrol = mii_rw(nic, np->phyaddr, MII_BMCR, MII_READ);
+		/* FIXME: 100 tries seem excessive */
+		if (tries++ > 100)
+			return -1;
+	}
+	return 0;
+}
+
+static int phy_init(struct nic *nic)
+{
+	u8 *base = (u8 *) BASE;
+	u32 phyinterface, phy_reserved, mii_status, mii_control,
+	    mii_control_1000, reg;
+
+	/* set advertise register */
+	reg = mii_rw(nic, np->phyaddr, MII_ADVERTISE, MII_READ);
+	reg |=
+	    (ADVERTISE_10HALF | ADVERTISE_10FULL | ADVERTISE_100HALF |
+	     ADVERTISE_100FULL | 0x800 | 0x400);
+	if (mii_rw(nic, np->phyaddr, MII_ADVERTISE, reg)) {
+		printf("phy write to advertise failed.\n");
+		return PHY_ERROR;
+	}
+
+	/* get phy interface type */
+	phyinterface = readl(base + NvRegPhyInterface);
+
+	/* see if gigabit phy */
+	mii_status = mii_rw(nic, np->phyaddr, MII_BMSR, MII_READ);
+
+	if (mii_status & PHY_GIGABIT) {
+		np->gigabit = PHY_GIGABIT;
+		mii_control_1000 =
+		    mii_rw(nic, np->phyaddr, MII_1000BT_CR, MII_READ);
+		mii_control_1000 &= ~ADVERTISE_1000HALF;
+		if (phyinterface & PHY_RGMII)
+			mii_control_1000 |= ADVERTISE_1000FULL;
+		else
+			mii_control_1000 &= ~ADVERTISE_1000FULL;
+
+		if (mii_rw
+		    (nic, np->phyaddr, MII_1000BT_CR, mii_control_1000)) {
+			printf("phy init failed.\n");
+			return PHY_ERROR;
+		}
+	} else
+		np->gigabit = 0;
+
+	/* reset the phy */
+	if (phy_reset(nic)) {
+		printf("phy reset failed\n");
+		return PHY_ERROR;
+	}
+
+	/* phy vendor specific configuration */
+	if ((np->phy_oui == PHY_OUI_CICADA) && (phyinterface & PHY_RGMII)) {
+		phy_reserved =
+		    mii_rw(nic, np->phyaddr, MII_RESV1, MII_READ);
+		phy_reserved &= ~(PHY_INIT1 | PHY_INIT2);
+		phy_reserved |= (PHY_INIT3 | PHY_INIT4);
+		if (mii_rw(nic, np->phyaddr, MII_RESV1, phy_reserved)) {
+			printf("phy init failed.\n");
+			return PHY_ERROR;
+		}
+		phy_reserved =
+		    mii_rw(nic, np->phyaddr, MII_NCONFIG, MII_READ);
+		phy_reserved |= PHY_INIT5;
+		if (mii_rw(nic, np->phyaddr, MII_NCONFIG, phy_reserved)) {
+			printf("phy init failed.\n");
+			return PHY_ERROR;
+		}
+	}
+	if (np->phy_oui == PHY_OUI_CICADA) {
+		phy_reserved =
+		    mii_rw(nic, np->phyaddr, MII_SREVISION, MII_READ);
+		phy_reserved |= PHY_INIT6;
+		if (mii_rw(nic, np->phyaddr, MII_SREVISION, phy_reserved)) {
+			printf("phy init failed.\n");
+			return PHY_ERROR;
+		}
+	}
+
+	/* restart auto negotiation */
+	mii_control = mii_rw(nic, np->phyaddr, MII_BMCR, MII_READ);
+	mii_control |= (BMCR_ANRESTART | BMCR_ANENABLE);
+	if (mii_rw(nic, np->phyaddr, MII_BMCR, mii_control)) {
+		return PHY_ERROR;
+	}
+
+	return 0;
+}
+
 static void start_rx(struct nic *nic __unused)
 {
 	u8 *base = (u8 *) BASE;
@@ -497,11 +698,12 @@ static void txrx_reset(struct nic *nic __unused)
 	u8 *base = (u8 *) BASE;
 
 	dprintf(("txrx_reset\n"));
-	writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET,
+	writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->desc_ver,
 	       base + NvRegTxRxControl);
+
 	pci_push(base);
 	udelay(NV_TXRX_RESET_DELAY);
-	writel(NVREG_TXRXCTL_BIT2, base + NvRegTxRxControl);
+	writel(NVREG_TXRXCTL_BIT2 | np->desc_ver, base + NvRegTxRxControl);
 	pci_push(base);
 }
 
@@ -519,9 +721,9 @@ static int alloc_rx(struct nic *nic __unused)
 		//int nr = refill_rx % RX_RING;
 		rx_ring[i].PacketBuffer =
 		    virt_to_le32desc(&rxb[i * RX_NIC_BUFSIZE]);
-		rx_ring[i].Length = cpu_to_le16(RX_NIC_BUFSIZE);
 		wmb();
-		rx_ring[i].Flags = cpu_to_le16(NV_RX_AVAIL);
+		rx_ring[i].FlagLen =
+		    cpu_to_le32(RX_NIC_BUFSIZE | NV_RX_AVAIL);
 		/*      printf("alloc_rx: Packet  %d marked as Available\n",
 		   refill_rx); */
 		refill_rx++;
@@ -534,8 +736,67 @@ static int alloc_rx(struct nic *nic __unused)
 
 static int update_linkspeed(struct nic *nic)
 {
-	int adv, lpa, newdup;
+	int adv, lpa;
 	u32 newls;
+	int newdup = np->duplex;
+	u32 mii_status;
+	int retval = 0; 
+	u32 control_1000, status_1000, phyreg;
+	u8 *base = (u8 *) BASE;
+	int i;
+
+	/* BMSR_LSTATUS is latched, read it twice:
+	 * we want the current value.
+	 */
+	mii_rw(nic, np->phyaddr, MII_BMSR, MII_READ);
+	mii_status = mii_rw(nic, np->phyaddr, MII_BMSR, MII_READ);
+
+#if 1
+	//yhlu
+	for(i=0;i<30;i++) {
+		mii_status = mii_rw(nic, np->phyaddr, MII_BMSR, MII_READ);
+		if((mii_status & BMSR_LSTATUS) && (mii_status & BMSR_ANEGCOMPLETE)) break;
+		mdelay(100);
+	}
+#endif
+
+	if (!(mii_status & BMSR_LSTATUS)) {
+		printf
+		    ("no link detected by phy - falling back to 10HD.\n");
+		newls = NVREG_LINKSPEED_FORCE | NVREG_LINKSPEED_10;
+		newdup = 0;
+		retval = 0;
+		goto set_speed;
+	}
+
+	/* check auto negotiation is complete */
+	if (!(mii_status & BMSR_ANEGCOMPLETE)) {
+		/* still in autonegotiation - configure nic for 10 MBit HD and wait. */
+		newls = NVREG_LINKSPEED_FORCE | NVREG_LINKSPEED_10;
+		newdup = 0;
+		retval = 0;
+		printf("autoneg not completed - falling back to 10HD.\n");
+		goto set_speed;
+	}
+
+	retval = 1;
+	if (np->gigabit == PHY_GIGABIT) {
+		control_1000 =
+		    mii_rw(nic, np->phyaddr, MII_1000BT_CR, MII_READ);
+		status_1000 =
+		    mii_rw(nic, np->phyaddr, MII_1000BT_SR, MII_READ);
+
+		if ((control_1000 & ADVERTISE_1000FULL) &&
+		    (status_1000 & LPA_1000FULL)) {
+			printf
+			    ("update_linkspeed: GBit ethernet detected.\n");
+			newls =
+			    NVREG_LINKSPEED_FORCE | NVREG_LINKSPEED_1000;
+			newdup = 1;
+			goto set_speed;
+		}
+	}
+
 	adv = mii_rw(nic, np->phyaddr, MII_ADVERTISE, MII_READ);
 	lpa = mii_rw(nic, np->phyaddr, MII_LPA, MII_READ);
 	dprintf(("update_linkspeed: PHY advertises 0x%hX, lpa 0x%hX.\n",
@@ -560,30 +821,81 @@ static int update_linkspeed(struct nic *nic)
 		newls = NVREG_LINKSPEED_FORCE | NVREG_LINKSPEED_10;
 		newdup = 0;
 	}
-	if (np->duplex != newdup || np->linkspeed != newls) {
-		np->duplex = newdup;
-		np->linkspeed = newls;
-		return 1;
+
+      set_speed:
+	if (np->duplex == newdup && np->linkspeed == newls)
+		return retval;
+
+	dprintf(("changing link setting from %d/%s to %d/%s.\n",
+	       np->linkspeed, np->duplex ? "Full-Duplex": "Half-Duplex", newls, newdup ? "Full-Duplex": "Half-Duplex"));
+
+	np->duplex = newdup;
+	np->linkspeed = newls;
+
+	if (np->gigabit == PHY_GIGABIT) {
+		phyreg = readl(base + NvRegRandomSeed);
+		phyreg &= ~(0x3FF00);
+		if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_10)
+			phyreg |= NVREG_RNDSEED_FORCE3;
+		else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_100)
+			phyreg |= NVREG_RNDSEED_FORCE2;
+		else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_1000)
+			phyreg |= NVREG_RNDSEED_FORCE;
+		writel(phyreg, base + NvRegRandomSeed);
 	}
-	return 0;
-}
 
+	phyreg = readl(base + NvRegPhyInterface);
+	phyreg &= ~(PHY_HALF | PHY_100 | PHY_1000);
+	if (np->duplex == 0)
+		phyreg |= PHY_HALF;
+	if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_100)
+		phyreg |= PHY_100;
+	else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_1000)
+		phyreg |= PHY_1000;
+	writel(phyreg, base + NvRegPhyInterface);
 
+	writel(NVREG_MISC1_FORCE | (np->duplex ? 0 : NVREG_MISC1_HD),
+	       base + NvRegMisc1);
+	pci_push(base);
+	writel(np->linkspeed, base + NvRegLinkSpeed);
+	pci_push(base);
+
+	return retval;
+}
+
+#if 0 /* Not used */
+static void nv_linkchange(struct nic *nic)
+{
+	if (update_linkspeed(nic)) {
+//                if (netif_carrier_ok(nic)) {
+		stop_rx();
+//=                } else {
+		//                      netif_carrier_on(dev);
+		//                    printk(KERN_INFO "%s: link up.\n", dev->name);
+		//          }
+		start_rx(nic);
+	} else {
+		//        if (netif_carrier_ok(dev)) {
+		//              netif_carrier_off(dev);
+		//            printk(KERN_INFO "%s: link down.\n", dev->name);
+		stop_rx();
+		//  }
+	}
+}
+#endif
 
 static int init_ring(struct nic *nic)
 {
 	int i;
 
 	np->next_tx = np->nic_tx = 0;
-	for (i = 0; i < TX_RING; i++) {
-		tx_ring[i].Flags = 0;
-	}
+	for (i = 0; i < TX_RING; i++)
+		tx_ring[i].FlagLen = 0;
 
 	np->cur_rx = 0;
 	np->refill_rx = 0;
-	for (i = 0; i < RX_RING; i++) {
-		rx_ring[i].Flags = 0;
-	}
+	for (i = 0; i < RX_RING; i++)
+		rx_ring[i].FlagLen = 0;
 	return alloc_rx(nic);
 }
 
@@ -637,15 +949,21 @@ static int forcedeth_reset(struct nic *nic)
 	writel(0, base + NvRegMulticastMaskA);
 	writel(0, base + NvRegMulticastMaskB);
 	writel(0, base + NvRegPacketFilterFlags);
+
+	writel(0, base + NvRegTransmitterControl);
+	writel(0, base + NvRegReceiverControl);
+
 	writel(0, base + NvRegAdapterControl);
+
+	/* 2) initialize descriptor rings */
+	oom = init_ring(nic);
+
 	writel(0, base + NvRegLinkSpeed);
 	writel(0, base + NvRegUnknownTransmitterReg);
 	txrx_reset(nic);
 	writel(0, base + NvRegUnknownSetupReg6);
 
-	/* 2) initialize descriptor rings */
 	np->in_shutdown = 0;
-	oom = init_ring(nic);
 
 	/* 3) set mac address */
 	{
@@ -661,51 +979,40 @@ static int forcedeth_reset(struct nic *nic)
 		writel(mac[1], base + NvRegMacAddrB);
 	}
 
-	/* 4) continue setup */
+	/* 4) give hw rings */
+	writel((u32) virt_to_le32desc(&rx_ring[0]),
+	       base + NvRegRxRingPhysAddr);
+	writel((u32) virt_to_le32desc(&tx_ring[0]),
+	       base + NvRegTxRingPhysAddr);
+
+	writel(((RX_RING - 1) << NVREG_RINGSZ_RXSHIFT) +
+	       ((TX_RING - 1) << NVREG_RINGSZ_TXSHIFT),
+	       base + NvRegRingSizes);
+
+	/* 5) continue setup */
 	np->linkspeed = NVREG_LINKSPEED_FORCE | NVREG_LINKSPEED_10;
 	np->duplex = 0;
+	writel(np->linkspeed, base + NvRegLinkSpeed);
 	writel(NVREG_UNKSETUP3_VAL1, base + NvRegUnknownSetupReg3);
-	writel(0, base + NvRegTxRxControl);
+	writel(np->desc_ver, base + NvRegTxRxControl);
 	pci_push(base);
-	writel(NVREG_TXRXCTL_BIT1, base + NvRegTxRxControl);
-
+	writel(NVREG_TXRXCTL_BIT1 | np->desc_ver, base + NvRegTxRxControl);
 	reg_delay(NvRegUnknownSetupReg5, NVREG_UNKSETUP5_BIT31,
 		  NVREG_UNKSETUP5_BIT31, NV_SETUP5_DELAY,
 		  NV_SETUP5_DELAYMAX,
 		  "open: SetupReg5, Bit 31 remained off\n");
-	writel(0, base + NvRegUnknownSetupReg4);
-
-	/* 5) Find a suitable PHY */
-	writel(NVREG_MIISPEED_BIT8 | NVREG_MIIDELAY, base + NvRegMIISpeed);
-	for (i = 1; i < 32; i++) {
-		int id1, id2;
-
-		id1 = mii_rw(nic, i, MII_PHYSID1, MII_READ);
-		if (id1 < 0)
-			continue;
-		id2 = mii_rw(nic, i, MII_PHYSID2, MII_READ);
-		if (id2 < 0)
-			continue;
-		dprintf(("open: Found PHY %04x:%04x at address %d.\n",
-			 id1, id2, i));
-		np->phyaddr = i;
-
-		update_linkspeed(nic);
-
-		break;
-	}
-	if (i == 32) {
-		printf("open: failing due to lack of suitable PHY.\n");
-		ret = -1;
-		goto out_drain;
-	}
 
+	writel(0, base + NvRegUnknownSetupReg4);
+//       writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
+	writel(NVREG_MIISTAT_MASK2, base + NvRegMIIStatus);
+#if 0
 	printf("%d-Mbs Link, %s-Duplex\n",
 	       np->linkspeed & NVREG_LINKSPEED_10 ? 10 : 100,
 	       np->duplex ? "Full" : "Half");
+#endif
+
 	/* 6) continue setup */
-	writel(NVREG_MISC1_FORCE | (np->duplex ? 0 : NVREG_MISC1_HD),
-	       base + NvRegMisc1);
+	writel(NVREG_MISC1_FORCE | NVREG_MISC1_HD, base + NvRegMisc1);
 	writel(readl(base + NvRegTransmitterStatus),
 	       base + NvRegTransmitterStatus);
 	writel(NVREG_PFF_ALWAYS, base + NvRegPacketFilterFlags);
@@ -714,8 +1021,8 @@ static int forcedeth_reset(struct nic *nic)
 	writel(readl(base + NvRegReceiverStatus),
 	       base + NvRegReceiverStatus);
 
-	/* FIXME: I cheated and used the calculator to get a random number */
-	i = 75963081;
+	/* Get a random number */
+	i = random();
 	writel(NVREG_RNDSEED_FORCE | (i & NVREG_RNDSEED_MASK),
 	       base + NvRegRandomSeed);
 	writel(NVREG_UNKSETUP1_VAL, base + NvRegUnknownSetupReg1);
@@ -724,36 +1031,24 @@ static int forcedeth_reset(struct nic *nic)
 	writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
 	writel((np->
 		phyaddr << NVREG_ADAPTCTL_PHYSHIFT) |
-	       NVREG_ADAPTCTL_PHYVALID, base + NvRegAdapterControl);
+	       NVREG_ADAPTCTL_PHYVALID | NVREG_ADAPTCTL_RUNNING,
+	       base + NvRegAdapterControl);
+	writel(NVREG_MIISPEED_BIT8 | NVREG_MIIDELAY, base + NvRegMIISpeed);
 	writel(NVREG_UNKSETUP4_VAL, base + NvRegUnknownSetupReg4);
 	writel(NVREG_WAKEUPFLAGS_VAL, base + NvRegWakeUpFlags);
 
-	/* 7) start packet processing */
-	writel((u32) virt_to_le32desc(&rx_ring[0]),
-	       base + NvRegRxRingPhysAddr);
-	writel((u32) virt_to_le32desc(&tx_ring[0]),
-	       base + NvRegTxRingPhysAddr);
-
-
-	writel(((RX_RING - 1) << NVREG_RINGSZ_RXSHIFT) +
-	       ((TX_RING - 1) << NVREG_RINGSZ_TXSHIFT),
-	       base + NvRegRingSizes);
-
 	i = readl(base + NvRegPowerState);
-	if ((i & NVREG_POWERSTATE_POWEREDUP) == 0) {
+	if ((i & NVREG_POWERSTATE_POWEREDUP) == 0)
 		writel(NVREG_POWERSTATE_POWEREDUP | i,
 		       base + NvRegPowerState);
-	}
+
 	pci_push(base);
 	udelay(10);
 	writel(readl(base + NvRegPowerState) | NVREG_POWERSTATE_VALID,
 	       base + NvRegPowerState);
-	writel(NVREG_ADAPTCTL_RUNNING, base + NvRegAdapterControl);
 
 	writel(0, base + NvRegIrqMask);
 	pci_push(base);
-	writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
-	pci_push(base);
 	writel(NVREG_MIISTAT_MASK2, base + NvRegMIIStatus);
 	writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
 	pci_push(base);
@@ -768,22 +1063,32 @@ static int forcedeth_reset(struct nic *nic)
 	       base + NvRegPacketFilterFlags);
 
 	set_multicast(nic);
+	/* One manual link speed update: Interrupts are enabled, future link
+	 * speed changes cause interrupts and are handled by nv_link_irq().
+	 */
+	{
+		u32 miistat;
+		miistat = readl(base + NvRegMIIStatus);
+		writel(NVREG_MIISTAT_MASK, base + NvRegMIIStatus);
+		dprintf(("startup: got 0x%hX.\n", miistat));
+	}
+	ret = update_linkspeed(nic);
+
 	//start_rx(nic);
 	start_tx(nic);
 
-	if (!
-	    (mii_rw(nic, np->phyaddr, MII_BMSR, MII_READ) &
-	     BMSR_ANEGCOMPLETE)) {
+	if (ret) {
+		//Start Connection netif_carrier_on(dev);
+	} else {
 		printf("no link during initialization.\n");
 	}
 
-	udelay(10000);
-      out_drain:
 	return ret;
 }
 
-//extern void hex_dump(const char *data, const unsigned int len);
-
+/* 
+ * extern void hex_dump(const char *data, const unsigned int len);
+*/
 /**************************************************************************
 POLL - Wait for a frame
 ***************************************************************************/
@@ -793,26 +1098,35 @@ static int forcedeth_poll(struct nic *nic, int retrieve)
 	/* nic->packet should contain data on return */
 	/* nic->packetlen should contain length of data */
 
-	struct ring_desc *prd;
 	int len;
 	int i;
+	u32 Flags;
 
 	i = np->cur_rx % RX_RING;
-	prd = &rx_ring[i];
 
-	if ( ! (prd->Flags & cpu_to_le16(NV_RX_DESCRIPTORVALID)) ) {
-	  return 0;
+	Flags = le32_to_cpu(rx_ring[i].FlagLen);
+	len = nv_descr_getlength(&rx_ring[i], np->desc_ver);
+
+	if (Flags & NV_RX_AVAIL)
+		return 0;	/* still owned by hardware, */
+
+	if (np->desc_ver == DESC_VER_1) {
+		if (!(Flags & NV_RX_DESCRIPTORVALID))
+			return 0;
+	} else {
+		if (!(Flags & NV_RX2_DESCRIPTORVALID))
+			return 0;
 	}
 
-	if ( ! retrieve ) return 1;
+	if (!retrieve)
+		return 1;
 
 	/* got a valid packet - forward it to the network core */
-	len = cpu_to_le16(prd->Length);
 	nic->packetlen = len;
-	//hex_dump(rxb + (i * RX_NIC_BUFSIZE), len);
-	memcpy(nic->packet, rxb +
-	       (i * RX_NIC_BUFSIZE), nic->packetlen);
-
+	memcpy(nic->packet, rxb + (i * RX_NIC_BUFSIZE), nic->packetlen);
+/*
+ * 	hex_dump(rxb + (i * RX_NIC_BUFSIZE), len);
+*/
 	wmb();
 	np->cur_rx++;
 	alloc_rx(nic);
@@ -831,7 +1145,6 @@ static void forcedeth_transmit(struct nic *nic, const char *d,	/* Destination */
 	/* send the packet to destination */
 	u8 *ptxb;
 	u16 nstype;
-	//u16 status;
 	u8 *base = (u8 *) BASE;
 	int nr = np->next_tx % TX_RING;
 
@@ -851,14 +1164,12 @@ static void forcedeth_transmit(struct nic *nic, const char *d,	/* Destination */
 		ptxb[s++] = '\0';
 
 	tx_ring[nr].PacketBuffer = (u32) virt_to_le32desc(ptxb);
-	tx_ring[nr].Length = cpu_to_le16(s - 1);
 
 	wmb();
-	tx_ring[nr].Flags = np->tx_flags;
+	tx_ring[nr].FlagLen = cpu_to_le32((s - 1) | np->tx_flags);
 
-	writel(NVREG_TXRXCTL_KICK, base + NvRegTxRxControl);
+	writel(NVREG_TXRXCTL_KICK | np->desc_ver, base + NvRegTxRxControl);
 	pci_push(base);
-	tx_ring[nr].Flags = np->tx_flags;
 	np->next_tx++;
 }
 
@@ -896,16 +1207,17 @@ static void forcedeth_disable ( struct nic *nic __unused ) {
 /**************************************************************************
 IRQ - Enable, Disable, or Force interrupts
 ***************************************************************************/
-static void forcedeth_irq(struct nic *nic __unused, irq_action_t action __unused)
+static void forcedeth_irq(struct nic *nic __unused,
+			  irq_action_t action __unused)
 {
-  switch ( action ) {
-  case DISABLE :
-    break;
-  case ENABLE :
-    break;
-  case FORCE :
-    break;
-  }
+	switch (action) {
+	case DISABLE:
+		break;
+	case ENABLE:
+		break;
+	case FORCE:
+		break;
+	}
 }
 
 static struct nic_operations forcedeth_operations = {
@@ -916,14 +1228,6 @@ static struct nic_operations forcedeth_operations = {
 
 };
 
-static struct pci_id forcedeth_nics[] = {
-	PCI_ROM(0x10de, 0x01C3, "nforce", "nForce Ethernet Controller"),
-	PCI_ROM(0x10de, 0x0066, "nforce2", "nForce2 Ethernet Controller"),
-	PCI_ROM(0x10de, 0x00D6, "nforce3", "nForce3 Ethernet Controller"),
-};
-
-PCI_DRIVER ( forcedeth_driver, forcedeth_nics, PCI_NO_CLASS );
-
 /**************************************************************************
 PROBE - Look for an adapter, this routine's visible to the outside
 ***************************************************************************/
@@ -935,6 +1239,7 @@ static int forcedeth_probe ( struct nic *nic, struct pci_device *pci ) {
 	unsigned long addr;
 	int sz;
 	u8 *base;
+	int i;
 
 	if (pci->ioaddr == 0)
 		return 0;
@@ -956,6 +1261,15 @@ static int forcedeth_probe ( struct nic *nic, struct pci_device *pci ) {
 	BASE = (unsigned long) ioremap(addr, sz);
 	if (!BASE)
 		return 0;
+
+	/* handle different descriptor versions */
+	if (pci->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_1 ||
+	    pci->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_2 ||
+	    pci->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_3)
+		np->desc_ver = DESC_VER_1;
+	else
+		np->desc_ver = DESC_VER_2;
+
 	//rx_ring[0] = rx_ring;
 	//tx_ring[0] = tx_ring; 
 
@@ -992,36 +1306,121 @@ static int forcedeth_probe ( struct nic *nic, struct pci_device *pci ) {
 #endif
 	printf("%s: MAC Address %!, ", pci->name, nic->node_addr);
 
-	np->tx_flags =
-	    cpu_to_le16(NV_TX_LASTPACKET | NV_TX_LASTPACKET1 |
-			NV_TX_VALID);
-	switch (pci->device_id) {
-	case 0x01C3:		// nforce
-		np->irqmask = NVREG_IRQMASK_WANTED_2;
-		np->irqmask |= NVREG_IRQ_TIMER;
-		break;
-	case 0x0066:		// nforce2
-		np->tx_flags |= cpu_to_le16(NV_TX_LASTPACKET1);
-		np->irqmask = NVREG_IRQMASK_WANTED_2;
-		np->irqmask |= NVREG_IRQ_TIMER;
-		break;
-	case 0x00D6:		// nforce3
-		np->tx_flags |= cpu_to_le16(NV_TX_LASTPACKET1);
-		np->irqmask = NVREG_IRQMASK_WANTED_2;
-		np->irqmask |= NVREG_IRQ_TIMER;
-
-	}
+ 	/* disable WOL */
+	writel(0, base + NvRegWakeUpFlags);
+ 	np->wolenabled = 0;
+	
+ 	if (np->desc_ver == DESC_VER_1) {
+ 		np->tx_flags = NV_TX_LASTPACKET | NV_TX_VALID;
+ 	} else {
+ 		np->tx_flags = NV_TX2_LASTPACKET | NV_TX2_VALID;
+ 	}
+
+  	switch (pci->device_id) {
+  	case 0x01C3:		// nforce
+ 		// DEV_IRQMASK_1|DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
+ 		np->irqmask = NVREG_IRQMASK_WANTED_2 | NVREG_IRQ_TIMER;
+		//              np->need_linktimer = 1;
+		//              np->link_timeout = jiffies + LINK_TIMEOUT;
+  		break;
+ 	case 0x0066:
+ 		/* Fall Through */
+ 	case 0x00D6:
+ 		// DEV_NEED_LASTPACKET1|DEV_IRQMASK_2|DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER
+  		np->irqmask = NVREG_IRQMASK_WANTED_2;
+  		np->irqmask |= NVREG_IRQ_TIMER;
+		//              np->need_linktimer = 1;
+		//              np->link_timeout = jiffies + LINK_TIMEOUT;
+ 		if (np->desc_ver == DESC_VER_1)
+ 			np->tx_flags |= NV_TX_LASTPACKET1;
+ 		else
+ 			np->tx_flags |= NV_TX2_LASTPACKET1;
+  		break;
+ 	case 0x0086:
+ 		/* Fall Through */
+ 	case 0x008c:
+ 		/* Fall Through */
+ 	case 0x00e6:
+ 		/* Fall Through */
+ 	case 0x00df:
+		/* Fall Through */
+ 	case 0x0056:
+ 		/* Fall Through */
+ 	case 0x0057:
+ 		/* Fall Through */
+ 	case 0x0037:
+ 		/* Fall Through */
+ 	case 0x0038:
+ 		//DEV_NEED_LASTPACKET1|DEV_IRQMASK_2|DEV_NEED_TIMERIRQ
+  		np->irqmask = NVREG_IRQMASK_WANTED_2;
+  		np->irqmask |= NVREG_IRQ_TIMER;
+		//              np->need_linktimer = 1;
+		//              np->link_timeout = jiffies + LINK_TIMEOUT;
+ 		if (np->desc_ver == DESC_VER_1)
+ 			np->tx_flags |= NV_TX_LASTPACKET1;
+ 		else
+ 			np->tx_flags |= NV_TX2_LASTPACKET1;
+ 		break;
+ 	default:
+ 		printf
+			("Your card was undefined in this driver.  Review driver_data in Linux driver and send a patch\n");
+ 	}
+	
+ 	/* find a suitable phy */
+ 	for (i = 1; i < 32; i++) {
+ 		int id1, id2;
+ 		id1 = mii_rw(nic, i, MII_PHYSID1, MII_READ);
+ 		if (id1 < 0 || id1 == 0xffff)
+ 			continue;
+ 		id2 = mii_rw(nic, i, MII_PHYSID2, MII_READ);
+ 		if (id2 < 0 || id2 == 0xffff)
+ 			continue;
+ 		id1 = (id1 & PHYID1_OUI_MASK) << PHYID1_OUI_SHFT;
+ 		id2 = (id2 & PHYID2_OUI_MASK) >> PHYID2_OUI_SHFT;
+ 		dprintf
+			(("%s: open: Found PHY %hX:%hX at address %d.\n",
+			  pci->name, id1, id2, i));
+ 		np->phyaddr = i;
+ 		np->phy_oui = id1 | id2;
+ 		break;
+ 	}
+ 	if (i == 32) {
+ 		/* PHY in isolate mode? No phy attached and user wants to
+ 		 * test loopback? Very odd, but can be correct.
+ 		 */
+ 		printf
+			("%s: open: Could not find a valid PHY.\n", pci->name);
+ 	}
+	
+ 	if (i != 32) {
+ 		/* reset it */
+ 		phy_init(nic);
+ 	}
+	
 	dprintf(("%s: forcedeth.c: subsystem: %hX:%hX bound to %s\n",
 		 pci->name, pci->vendor, pci->dev_id, pci->name));
+	if(!forcedeth_reset(nic)) return 0; // no valid link
 
-	forcedeth_reset(nic);
-//      if (board_found && valid_link)
 	/* point to NIC specific routines */
 	nic->nic_op	= &forcedeth_operations;
 	return 1;
-//      }
-	/* else */
 }
 
+static struct pci_id forcedeth_nics[] = {
+PCI_ROM(0x10de, 0x01C3, "nforce", "nForce NVENET_1 Ethernet Controller"),
+PCI_ROM(0x10de, 0x0066, "nforce2", "nForce NVENET_2 Ethernet Controller"),
+PCI_ROM(0x10de, 0x00D6, "nforce3", "nForce NVENET_3 Ethernet Controller"),
+PCI_ROM(0x10de, 0x0086, "nforce4", "nForce NVENET_4 Ethernet Controller"),
+PCI_ROM(0x10de, 0x008c, "nforce5", "nForce NVENET_5 Ethernet Controller"),
+PCI_ROM(0x10de, 0x00e6, "nforce6", "nForce NVENET_6 Ethernet Controller"),
+PCI_ROM(0x10de, 0x00df, "nforce7", "nForce NVENET_7 Ethernet Controller"),
+PCI_ROM(0x10de, 0x0056, "nforce8", "nForce NVENET_8 Ethernet Controller"),
+PCI_ROM(0x10de, 0x0057, "nforce9", "nForce NVENET_9 Ethernet Controller"),
+PCI_ROM(0x10de, 0x0037, "nforce10", "nForce NVENET_10 Ethernet Controller"),
+PCI_ROM(0x10de, 0x0038, "nforce11", "nForce NVENET_11 Ethernet Controller"),
+};
+
+PCI_DRIVER ( forcedeth_driver, forcedeth_nics, PCI_NO_CLASS );
+
 DRIVER ( "forcedeth", nic_driver, pci_driver, forcedeth_driver,
 	 forcedeth_probe, forcedeth_disable );
diff --git a/src/drivers/net/mtd80x.c b/src/drivers/net/mtd80x.c
index 3d974abc3..c7754a94f 100644
--- a/src/drivers/net/mtd80x.c
+++ b/src/drivers/net/mtd80x.c
@@ -30,13 +30,6 @@
 /* to get the PCI support functions, if this is a PCI NIC */
 #include "pci.h"
 
-typedef unsigned char u8;
-typedef signed char s8;
-typedef unsigned short u16;
-typedef signed short s16;
-typedef unsigned int u32;
-typedef signed int s32;
-
 /* Condensed operations for readability. */
 #define virt_to_le32desc(addr)  cpu_to_le32(virt_to_bus(addr))
 #define le32desc_to_virt(addr)  bus_to_virt(le32_to_cpu(addr))
diff --git a/src/drivers/net/natsemi.c b/src/drivers/net/natsemi.c
index 003b97983..e8f6d81c1 100644
--- a/src/drivers/net/natsemi.c
+++ b/src/drivers/net/natsemi.c
@@ -71,13 +71,6 @@
 
 #define NUM_RX_DESC    4              /* Number of Rx descriptor registers. */
 
-typedef uint8_t    u8;
-typedef int8_t     s8;
-typedef uint16_t   u16;
-typedef int16_t    s16;
-typedef uint32_t   u32;
-typedef int32_t    s32;
-
 /* helpful macroes if on a big_endian machine for changing byte order.
    not strictly needed on Intel */
 #define get_unaligned(ptr) (*(ptr))
@@ -611,7 +604,7 @@ natsemi_transmit(struct nic  *nic,
 		 const char  *p)     /* Packet */
 {
     u32 to, nstype;
-    u32 tx_status;
+    volatile u32 tx_status;
     
     /* Stop the transmitter */
     outl(TxOff, ioaddr + ChipCmd);
@@ -650,7 +643,7 @@ natsemi_transmit(struct nic  *nic,
 
     to = currticks() + TX_TIMEOUT;
 
-    while ((((volatile u32) tx_status=txd.cmdsts) & OWN) && (currticks() < to))
+    while (((tx_status=txd.cmdsts) & OWN) && (currticks() < to))
         /* wait */ ;
 
     if (currticks() >= to) {
diff --git a/src/drivers/net/ns83820.c b/src/drivers/net/ns83820.c
index d4fafb686..df9eec5a2 100755
--- a/src/drivers/net/ns83820.c
+++ b/src/drivers/net/ns83820.c
@@ -53,13 +53,6 @@
 #define dprintf(x)
 #endif
 
-typedef unsigned char u8;
-typedef signed char s8;
-typedef unsigned short u16;
-typedef signed short s16;
-typedef unsigned int u32;
-typedef signed int s32;
-
 #define HZ 100
 
 /* Condensed operations for readability. */
diff --git a/src/drivers/net/pcnet32.c b/src/drivers/net/pcnet32.c
index 5a0bb14cd..4255269bb 100644
--- a/src/drivers/net/pcnet32.c
+++ b/src/drivers/net/pcnet32.c
@@ -54,13 +54,6 @@
 #define drv_version "v1.3"
 #define drv_date "03-29-2004"
 
-typedef unsigned char u8;
-typedef signed char s8;
-typedef unsigned short u16;
-typedef signed short s16;
-typedef unsigned int u32;
-typedef signed int s32;
-
 static u32 ioaddr;		/* Globally used for the card's io address */
 static struct nic_operations pcnet32_operations;
 static struct pci_driver pcnet32_driver;
diff --git a/src/drivers/net/r8169.c b/src/drivers/net/r8169.c
index ad3b62bd6..427fad0f8 100644
--- a/src/drivers/net/r8169.c
+++ b/src/drivers/net/r8169.c
@@ -52,13 +52,6 @@
 #define drv_version "v1.6"
 #define drv_date "03-27-2004"
 
-typedef unsigned char u8;
-typedef signed char s8;
-typedef unsigned short u16;
-typedef signed short s16;
-typedef unsigned int u32;
-typedef signed int s32;
-
 #define HZ 1000
 
 static u32 ioaddr;
diff --git a/src/drivers/net/sis900.c b/src/drivers/net/sis900.c
index b5ba3f08b..c2cb94e87 100644
--- a/src/drivers/net/sis900.c
+++ b/src/drivers/net/sis900.c
@@ -1097,7 +1097,7 @@ sis900_transmit(struct nic  *nic,
                 const char  *p)     /* Packet */
 {
     u32 to, nstype;
-    u32 tx_status;
+    volatile u32 tx_status;
     
     /* Stop the transmitter */
     outl(TxDIS | inl(ioaddr + cr), ioaddr + cr);
@@ -1136,7 +1136,7 @@ sis900_transmit(struct nic  *nic,
 
     to = currticks() + TX_TIMEOUT;
 
-    while ((((volatile u32) tx_status=txd.cmdsts) & OWN) && (currticks() < to))
+    while (((tx_status=txd.cmdsts) & OWN) && (currticks() < to))
         /* wait */ ;
 
     if (currticks() >= to) {
diff --git a/src/drivers/net/sis900.h b/src/drivers/net/sis900.h
index 89aa3aa5a..e88e111d4 100644
--- a/src/drivers/net/sis900.h
+++ b/src/drivers/net/sis900.h
@@ -363,13 +363,6 @@ enum sis630_revision_id {
 
 #define NUM_RX_DESC     4              /* Number of Rx descriptor registers. */
 
-typedef unsigned char  u8;
-typedef   signed char  s8;
-typedef unsigned short u16;
-typedef   signed short s16;
-typedef unsigned int   u32;
-typedef   signed int   s32;
-
 /* Time in ticks before concluding the transmitter is hung. */
 #define TX_TIMEOUT       (4*TICKS_PER_SEC)
 
diff --git a/src/drivers/net/smc9000.c b/src/drivers/net/smc9000.c
index 7c6947777..43f04f061 100644
--- a/src/drivers/net/smc9000.c
+++ b/src/drivers/net/smc9000.c
@@ -29,9 +29,16 @@
 #define LINUX_OUT_MACROS 1
 #define SMC9000_DEBUG    0
 
+#if SMC9000_DEBUG > 1
+#define PRINTK2 printf
+#else
+#define PRINTK2(args...)
+#endif
+
 #include "etherboot.h"
 #include "nic.h"
 #include "isa.h"
+#include "timer.h"
 #include "smc9000.h"
 
 # define _outb outb
@@ -47,11 +54,449 @@ static const char       *chip_ids[ 15 ] =  {
    NULL,
    /* 7 */ "SMC91C100",
    /* 8 */ "SMC91C100FD",
-   NULL, NULL, NULL,
+   /* 9 */ "SMC91C11xFD",
+   NULL, NULL,
    NULL, NULL, NULL
 };
 static const char      smc91c96_id[] = "SMC91C96";
 
+/*------------------------------------------------------------
+ . Reads a register from the MII Management serial interface
+ .-------------------------------------------------------------*/
+static word smc_read_phy_register(int ioaddr, byte phyaddr, byte phyreg)
+{
+    int oldBank;
+    unsigned int i;
+    byte mask;
+    word mii_reg;
+    byte bits[64];
+    int clk_idx = 0;
+    int input_idx;
+    word phydata;
+
+    // 32 consecutive ones on MDO to establish sync
+    for (i = 0; i < 32; ++i)
+        bits[clk_idx++] = MII_MDOE | MII_MDO;
+
+    // Start code <01>
+    bits[clk_idx++] = MII_MDOE;
+    bits[clk_idx++] = MII_MDOE | MII_MDO;
+
+    // Read command <10>
+    bits[clk_idx++] = MII_MDOE | MII_MDO;
+    bits[clk_idx++] = MII_MDOE;
+
+    // Output the PHY address, msb first
+    mask = (byte)0x10;
+    for (i = 0; i < 5; ++i)
+    {
+        if (phyaddr & mask)
+            bits[clk_idx++] = MII_MDOE | MII_MDO;
+        else
+            bits[clk_idx++] = MII_MDOE;
+
+        // Shift to next lowest bit
+        mask >>= 1;
+    }
+
+    // Output the phy register number, msb first
+    mask = (byte)0x10;
+    for (i = 0; i < 5; ++i)
+    {
+        if (phyreg & mask)
+            bits[clk_idx++] = MII_MDOE | MII_MDO;
+        else
+            bits[clk_idx++] = MII_MDOE;
+
+        // Shift to next lowest bit
+        mask >>= 1;
+    }
+
+    // Tristate and turnaround (2 bit times)
+    bits[clk_idx++] = 0;
+    //bits[clk_idx++] = 0;
+
+    // Input starts at this bit time
+    input_idx = clk_idx;
+
+    // Will input 16 bits
+    for (i = 0; i < 16; ++i)
+        bits[clk_idx++] = 0;
+
+    // Final clock bit
+    bits[clk_idx++] = 0;
+
+    // Save the current bank
+    oldBank = inw( ioaddr+BANK_SELECT );
+
+    // Select bank 3
+    SMC_SELECT_BANK(ioaddr, 3);
+
+    // Get the current MII register value
+    mii_reg = inw( ioaddr+MII_REG );
+
+    // Turn off all MII Interface bits
+    mii_reg &= ~(MII_MDOE|MII_MCLK|MII_MDI|MII_MDO);
+
+    // Clock all 64 cycles
+    for (i = 0; i < sizeof(bits); ++i)
+    {
+        // Clock Low - output data
+        outw( mii_reg | bits[i], ioaddr+MII_REG );
+        udelay(50);
+
+
+        // Clock Hi - input data
+        outw( mii_reg | bits[i] | MII_MCLK, ioaddr+MII_REG );
+        udelay(50);
+        bits[i] |= inw( ioaddr+MII_REG ) & MII_MDI;
+    }
+
+    // Return to idle state
+    // Set clock to low, data to low, and output tristated
+    outw( mii_reg, ioaddr+MII_REG );
+    udelay(50);
+
+    // Restore original bank select
+    SMC_SELECT_BANK(ioaddr, oldBank);
+
+    // Recover input data
+    phydata = 0;
+    for (i = 0; i < 16; ++i)
+    {
+        phydata <<= 1;
+
+        if (bits[input_idx++] & MII_MDI)
+            phydata |= 0x0001;
+    }
+
+#if (SMC_DEBUG > 2 )
+        printf("smc_read_phy_register(): phyaddr=%x,phyreg=%x,phydata=%x\n",
+               phyaddr, phyreg, phydata);
+#endif
+
+        return(phydata);
+}
+
+
+/*------------------------------------------------------------
+ . Writes a register to the MII Management serial interface
+ .-------------------------------------------------------------*/
+static void smc_write_phy_register(int ioaddr,
+                                   byte phyaddr, byte phyreg, word phydata)
+{
+    int oldBank;
+    unsigned int i;
+    word mask;
+    word mii_reg;
+    byte bits[65];
+    int clk_idx = 0;
+
+    // 32 consecutive ones on MDO to establish sync
+    for (i = 0; i < 32; ++i)
+        bits[clk_idx++] = MII_MDOE | MII_MDO;
+
+    // Start code <01>
+    bits[clk_idx++] = MII_MDOE;
+    bits[clk_idx++] = MII_MDOE | MII_MDO;
+
+    // Write command <01>
+    bits[clk_idx++] = MII_MDOE;
+    bits[clk_idx++] = MII_MDOE | MII_MDO;
+
+    // Output the PHY address, msb first
+    mask = (byte)0x10;
+    for (i = 0; i < 5; ++i)
+    {
+        if (phyaddr & mask)
+            bits[clk_idx++] = MII_MDOE | MII_MDO;
+        else
+            bits[clk_idx++] = MII_MDOE;
+
+                // Shift to next lowest bit
+        mask >>= 1;
+    }
+
+    // Output the phy register number, msb first
+    mask = (byte)0x10;
+    for (i = 0; i < 5; ++i)
+    {
+        if (phyreg & mask)
+            bits[clk_idx++] = MII_MDOE | MII_MDO;
+        else
+            bits[clk_idx++] = MII_MDOE;
+
+        // Shift to next lowest bit
+        mask >>= 1;
+    }
+
+    // Tristate and turnaround (2 bit times)
+    bits[clk_idx++] = 0;
+    bits[clk_idx++] = 0;
+
+    // Write out 16 bits of data, msb first
+    mask = 0x8000;
+    for (i = 0; i < 16; ++i)
+    {
+        if (phydata & mask)
+            bits[clk_idx++] = MII_MDOE | MII_MDO;
+        else
+            bits[clk_idx++] = MII_MDOE;
+
+        // Shift to next lowest bit
+        mask >>= 1;
+    }
+
+    // Final clock bit (tristate)
+    bits[clk_idx++] = 0;
+
+    // Save the current bank
+    oldBank = inw( ioaddr+BANK_SELECT );
+
+    // Select bank 3
+    SMC_SELECT_BANK(ioaddr, 3);
+
+    // Get the current MII register value
+    mii_reg = inw( ioaddr+MII_REG );
+
+    // Turn off all MII Interface bits
+    mii_reg &= ~(MII_MDOE|MII_MCLK|MII_MDI|MII_MDO);
+
+    // Clock all cycles
+    for (i = 0; i < sizeof(bits); ++i)
+    {
+        // Clock Low - output data
+        outw( mii_reg | bits[i], ioaddr+MII_REG );
+        udelay(50);
+
+
+        // Clock Hi - input data
+        outw( mii_reg | bits[i] | MII_MCLK, ioaddr+MII_REG );
+        udelay(50);
+        bits[i] |= inw( ioaddr+MII_REG ) & MII_MDI;
+    }
+
+    // Return to idle state
+    // Set clock to low, data to low, and output tristated
+    outw( mii_reg, ioaddr+MII_REG );
+    udelay(50);
+
+    // Restore original bank select
+    SMC_SELECT_BANK(ioaddr, oldBank);
+
+#if (SMC_DEBUG > 2 )
+        printf("smc_write_phy_register(): phyaddr=%x,phyreg=%x,phydata=%x\n",
+               phyaddr, phyreg, phydata);
+#endif
+}
+
+
+/*------------------------------------------------------------
+ . Finds and reports the PHY address
+ .-------------------------------------------------------------*/
+static int smc_detect_phy(int ioaddr, byte *pphyaddr)
+{
+    word phy_id1;
+    word phy_id2;
+    int phyaddr;
+    int found = 0;
+
+    // Scan all 32 PHY addresses if necessary
+    for (phyaddr = 0; phyaddr < 32; ++phyaddr)
+    {
+        // Read the PHY identifiers
+        phy_id1  = smc_read_phy_register(ioaddr, phyaddr, PHY_ID1_REG);
+        phy_id2  = smc_read_phy_register(ioaddr, phyaddr, PHY_ID2_REG);
+
+        // Make sure it is a valid identifier
+        if ((phy_id2 > 0x0000) && (phy_id2 < 0xffff) &&
+             (phy_id1 > 0x0000) && (phy_id1 < 0xffff))
+        {
+            if ((phy_id1 != 0x8000) && (phy_id2 != 0x8000))
+            {
+                // Save the PHY's address
+                *pphyaddr = phyaddr;
+                found = 1;
+                break;
+            }
+        }
+    }
+
+    if (!found)
+    {
+        printf("No PHY found\n");
+        return(0);
+    }
+
+    // Set the PHY type
+    if ( (phy_id1 == 0x0016) && ((phy_id2 & 0xFFF0) == 0xF840 ) )
+    {
+        printf("PHY=LAN83C183 (LAN91C111 Internal)\n");
+    }
+
+    if ( (phy_id1 == 0x0282) && ((phy_id2 & 0xFFF0) == 0x1C50) )
+    {
+        printf("PHY=LAN83C180\n");
+    }
+
+    return(1);
+}
+
+/*------------------------------------------------------------
+ . Configures the specified PHY using Autonegotiation. Calls
+ . smc_phy_fixed() if the user has requested a certain config.
+ .-------------------------------------------------------------*/
+static void smc_phy_configure(int ioaddr)
+{
+    int timeout;
+    byte phyaddr;
+    word my_phy_caps; // My PHY capabilities
+    word my_ad_caps; // My Advertised capabilities
+    word status;
+    int failed = 0;
+    int rpc_cur_mode = RPC_DEFAULT;
+    int lastPhy18;
+
+    // Find the address and type of our phy
+    if (!smc_detect_phy(ioaddr, &phyaddr))
+    {
+        return;
+    }
+
+    // Reset the PHY, setting all other bits to zero
+    smc_write_phy_register(ioaddr, phyaddr, PHY_CNTL_REG, PHY_CNTL_RST);
+
+    // Wait for the reset to complete, or time out
+    timeout = 6; // Wait up to 3 seconds
+    while (timeout--)
+    {
+        if (!(smc_read_phy_register(ioaddr, phyaddr, PHY_CNTL_REG)
+              & PHY_CNTL_RST))
+        {
+            // reset complete
+            break;
+        }
+
+        mdelay(500); // wait 500 millisecs
+    }
+
+    if (timeout < 1)
+    {
+        PRINTK2("PHY reset timed out\n");
+        return;
+    }
+
+    // Read PHY Register 18, Status Output
+    lastPhy18 = smc_read_phy_register(ioaddr, phyaddr, PHY_INT_REG);
+
+    // Enable PHY Interrupts (for register 18)
+    // Interrupts listed here are disabled
+    smc_write_phy_register(ioaddr, phyaddr, PHY_MASK_REG,
+                           PHY_INT_LOSSSYNC | PHY_INT_CWRD | PHY_INT_SSD |
+                                   PHY_INT_ESD | PHY_INT_RPOL | PHY_INT_JAB |
+                                   PHY_INT_SPDDET | PHY_INT_DPLXDET);
+
+    /* Configure the Receive/Phy Control register */
+    SMC_SELECT_BANK(ioaddr, 0);
+    outw( rpc_cur_mode, ioaddr + RPC_REG );
+
+    // Copy our capabilities from PHY_STAT_REG to PHY_AD_REG
+    my_phy_caps = smc_read_phy_register(ioaddr, phyaddr, PHY_STAT_REG);
+    my_ad_caps  = PHY_AD_CSMA; // I am CSMA capable
+
+    if (my_phy_caps & PHY_STAT_CAP_T4)
+        my_ad_caps |= PHY_AD_T4;
+
+    if (my_phy_caps & PHY_STAT_CAP_TXF)
+        my_ad_caps |= PHY_AD_TX_FDX;
+
+    if (my_phy_caps & PHY_STAT_CAP_TXH)
+        my_ad_caps |= PHY_AD_TX_HDX;
+
+    if (my_phy_caps & PHY_STAT_CAP_TF)
+        my_ad_caps |= PHY_AD_10_FDX;
+
+    if (my_phy_caps & PHY_STAT_CAP_TH)
+        my_ad_caps |= PHY_AD_10_HDX;
+
+    // Update our Auto-Neg Advertisement Register
+    smc_write_phy_register(ioaddr, phyaddr, PHY_AD_REG, my_ad_caps);
+
+    PRINTK2("phy caps=%x\n", my_phy_caps);
+    PRINTK2("phy advertised caps=%x\n", my_ad_caps);
+
+    // Restart auto-negotiation process in order to advertise my caps
+    smc_write_phy_register( ioaddr, phyaddr, PHY_CNTL_REG,
+                            PHY_CNTL_ANEG_EN | PHY_CNTL_ANEG_RST );
+
+    // Wait for the auto-negotiation to complete.  This may take from
+    // 2 to 3 seconds.
+    // Wait for the reset to complete, or time out
+    timeout = 20; // Wait up to 10 seconds
+    while (timeout--)
+    {
+        status = smc_read_phy_register(ioaddr, phyaddr, PHY_STAT_REG);
+        if (status & PHY_STAT_ANEG_ACK)
+        {
+            // auto-negotiate complete
+            break;
+        }
+
+        mdelay(500); // wait 500 millisecs
+
+        // Restart auto-negotiation if remote fault
+        if (status & PHY_STAT_REM_FLT)
+        {
+            PRINTK2("PHY remote fault detected\n");
+
+            // Restart auto-negotiation
+            PRINTK2("PHY restarting auto-negotiation\n");
+            smc_write_phy_register( ioaddr, phyaddr, PHY_CNTL_REG,
+                                    PHY_CNTL_ANEG_EN | PHY_CNTL_ANEG_RST |
+                                    PHY_CNTL_SPEED | PHY_CNTL_DPLX);
+        }
+    }
+
+    if (timeout < 1)
+    {
+        PRINTK2("PHY auto-negotiate timed out\n");
+        failed = 1;
+    }
+
+    // Fail if we detected an auto-negotiate remote fault
+    if (status & PHY_STAT_REM_FLT)
+    {
+        PRINTK2("PHY remote fault detected\n");
+        failed = 1;
+    }
+
+    // Set our sysctl parameters to match auto-negotiation results
+    if ( lastPhy18 & PHY_INT_SPDDET )
+    {
+        PRINTK2("PHY 100BaseT\n");
+        rpc_cur_mode |= RPC_SPEED;
+    }
+    else
+    {
+        PRINTK2("PHY 10BaseT\n");
+        rpc_cur_mode &= ~RPC_SPEED;
+    }
+
+    if ( lastPhy18 & PHY_INT_DPLXDET )
+    {
+        PRINTK2("PHY Full Duplex\n");
+        rpc_cur_mode |= RPC_DPLX;
+    }
+    else
+    {
+        PRINTK2("PHY Half Duplex\n");
+        rpc_cur_mode &= ~RPC_DPLX;
+    }
+
+    // Re-Configure the Receive/Phy Control register
+    outw( rpc_cur_mode, ioaddr + RPC_REG );
+}
+
 /*
  * Function: smc_reset( int ioaddr )
  * Purpose:
@@ -476,6 +921,8 @@ static int smc9000_probe ( struct nic *nic, struct isa_device *isa ) {
 	   nic->ioaddr + CONFIG );
    }
 
+   smc_phy_configure(nic->ioaddr);
+ 
    nic->nic_op	= &smc9000_operations;
    return 1;
 }
diff --git a/src/drivers/net/smc9000.h b/src/drivers/net/smc9000.h
index ac7f91639..ffe5bbdb9 100644
--- a/src/drivers/net/smc9000.h
+++ b/src/drivers/net/smc9000.h
@@ -91,6 +91,24 @@ typedef unsigned long int		dword;
 #define	MCR		10
 /* 12 is reserved */
 
+// Receive/Phy Control Register
+/* BANK 0  */
+#define RPC_REG         0x000A
+#define RPC_SPEED       0x2000  // When 1 PHY is in 100Mbps mode.
+#define RPC_DPLX        0x1000  // When 1 PHY is in Full-Duplex Mode
+#define RPC_ANEG        0x0800  // When 1 PHY is in Auto-Negotiate Mode
+#define RPC_LSXA_SHFT   5       // Bits to shift LS2A,LS1A,LS0A to lsb
+#define RPC_LSXB_SHFT   2       // Bits to get LS2B,LS1B,LS0B to lsb
+#define RPC_LED_100_10  (0x00)  // LED = 100Mbps OR's with 10Mbps link detect
+#define RPC_LED_RES     (0x01)  // LED = Reserved
+#define RPC_LED_10      (0x02)  // LED = 10Mbps link detect
+#define RPC_LED_FD      (0x03)  // LED = Full Duplex Mode
+#define RPC_LED_TX_RX   (0x04)  // LED = TX or RX packet occurred
+#define RPC_LED_100     (0x05)  // LED = 100Mbps link dectect
+#define RPC_LED_TX      (0x06)  // LED = TX packet occurred
+#define RPC_LED_RX      (0x07)  // LED = RX packet occurred
+#define RPC_DEFAULT (RPC_ANEG | (RPC_LED_100 << RPC_LSXA_SHFT) | (RPC_LED_FD << RPC_LSXB_SHFT) | RPC_SPEED | RPC_DPLX)
+
 /* BANK 1 */
 #define CONFIG			0
 #define CFG_AUI_SELECT		0x100
@@ -151,6 +169,13 @@ typedef unsigned long int		dword;
 #define	MGMT		8
 #define	REVISION	10 /* ( hi: chip id   low: rev # ) */
 
+// Management Interface Register (MII)
+#define MII_REG         0x0008
+#define MII_MSK_CRS100  0x4000 // Disables CRS100 detection during tx half dup
+#define MII_MDOE        0x0008 // MII Output Enable
+#define MII_MCLK        0x0004 // MII Clock, pin MDCLK
+#define MII_MDI         0x0002 // MII Input, pin MDI
+#define MII_MDO         0x0001 // MII Output, pin MDO
 
 /* this is NOT on SMC9192 */
 #define	ERCV		12
@@ -186,6 +211,95 @@ typedef unsigned long int		dword;
 #define RS_ERRORS	(RS_ALGNERR | RS_BADCRC | RS_TOOLONG | RS_TOOSHORT)
 
 
+// PHY Register Addresses (LAN91C111 Internal PHY)
+
+// PHY Control Register
+#define PHY_CNTL_REG            0x00
+#define PHY_CNTL_RST            0x8000  // 1=PHY Reset
+#define PHY_CNTL_LPBK           0x4000  // 1=PHY Loopback
+#define PHY_CNTL_SPEED          0x2000  // 1=100Mbps, 0=10Mpbs
+#define PHY_CNTL_ANEG_EN        0x1000 // 1=Enable Auto negotiation
+#define PHY_CNTL_PDN            0x0800  // 1=PHY Power Down mode
+#define PHY_CNTL_MII_DIS        0x0400  // 1=MII 4 bit interface disabled
+#define PHY_CNTL_ANEG_RST       0x0200 // 1=Reset Auto negotiate
+#define PHY_CNTL_DPLX           0x0100  // 1=Full Duplex, 0=Half Duplex
+#define PHY_CNTL_COLTST         0x0080  // 1= MII Colision Test
+
+// PHY Status Register
+#define PHY_STAT_REG            0x01
+#define PHY_STAT_CAP_T4         0x8000  // 1=100Base-T4 capable
+#define PHY_STAT_CAP_TXF        0x4000  // 1=100Base-X full duplex capable
+#define PHY_STAT_CAP_TXH        0x2000  // 1=100Base-X half duplex capable
+#define PHY_STAT_CAP_TF         0x1000  // 1=10Mbps full duplex capable
+#define PHY_STAT_CAP_TH         0x0800  // 1=10Mbps half duplex capable
+#define PHY_STAT_CAP_SUPR       0x0040  // 1=recv mgmt frames with not preamble
+#define PHY_STAT_ANEG_ACK       0x0020  // 1=ANEG has completed
+#define PHY_STAT_REM_FLT        0x0010  // 1=Remote Fault detected
+#define PHY_STAT_CAP_ANEG       0x0008  // 1=Auto negotiate capable
+#define PHY_STAT_LINK           0x0004  // 1=valid link
+#define PHY_STAT_JAB            0x0002  // 1=10Mbps jabber condition
+#define PHY_STAT_EXREG          0x0001  // 1=extended registers implemented
+
+// PHY Identifier Registers
+#define PHY_ID1_REG             0x02    // PHY Identifier 1
+#define PHY_ID2_REG             0x03    // PHY Identifier 2
+
+// PHY Auto-Negotiation Advertisement Register
+#define PHY_AD_REG              0x04
+#define PHY_AD_NP               0x8000  // 1=PHY requests exchange of Next Page
+#define PHY_AD_ACK              0x4000  // 1=got link code word from remote
+#define PHY_AD_RF               0x2000  // 1=advertise remote fault
+#define PHY_AD_T4               0x0200  // 1=PHY is capable of 100Base-T4
+#define PHY_AD_TX_FDX           0x0100  // 1=PHY is capable of 100Base-TX FDPLX
+#define PHY_AD_TX_HDX           0x0080  // 1=PHY is capable of 100Base-TX HDPLX
+#define PHY_AD_10_FDX           0x0040  // 1=PHY is capable of 10Base-T FDPLX
+#define PHY_AD_10_HDX           0x0020  // 1=PHY is capable of 10Base-T HDPLX
+#define PHY_AD_CSMA             0x0001  // 1=PHY is capable of 802.3 CMSA
+
+// PHY Auto-negotiation Remote End Capability Register
+#define PHY_RMT_REG             0x05
+// Uses same bit definitions as PHY_AD_REG
+
+// PHY Configuration Register 1
+#define PHY_CFG1_REG            0x10
+#define PHY_CFG1_LNKDIS         0x8000  // 1=Rx Link Detect Function disabled
+#define PHY_CFG1_XMTDIS         0x4000  // 1=TP Transmitter Disabled
+#define PHY_CFG1_XMTPDN         0x2000  // 1=TP Transmitter Powered Down
+#define PHY_CFG1_BYPSCR         0x0400  // 1=Bypass scrambler/descrambler
+#define PHY_CFG1_UNSCDS         0x0200  // 1=Unscramble Idle Reception Disable
+#define PHY_CFG1_EQLZR          0x0100  // 1=Rx Equalizer Disabled
+#define PHY_CFG1_CABLE          0x0080  // 1=STP(150ohm), 0=UTP(100ohm)
+#define PHY_CFG1_RLVL0          0x0040  // 1=Rx Squelch level reduced by 4.5db
+#define PHY_CFG1_TLVL_SHIFT     2       // Transmit Output Level Adjust
+#define PHY_CFG1_TLVL_MASK      0x003C
+#define PHY_CFG1_TRF_MASK       0x0003  // Transmitter Rise/Fall time
+
+
+// PHY Configuration Register 2
+#define PHY_CFG2_REG            0x11
+#define PHY_CFG2_APOLDIS        0x0020  // 1=Auto Polarity Correction disabled
+#define PHY_CFG2_JABDIS         0x0010  // 1=Jabber disabled
+#define PHY_CFG2_MREG           0x0008  // 1=Multiple register access (MII mgt)
+#define PHY_CFG2_INTMDIO        0x0004  // 1=Interrupt signaled with MDIO pulseo
+
+// PHY Status Output (and Interrupt status) Register
+#define PHY_INT_REG             0x12    // Status Output (Interrupt Status)
+#define PHY_INT_INT             0x8000  // 1=bits have changed since last read
+#define PHY_INT_LNKFAIL         0x4000  // 1=Link Not detected
+#define PHY_INT_LOSSSYNC        0x2000  // 1=Descrambler has lost sync
+#define PHY_INT_CWRD            0x1000  // 1=Invalid 4B5B code detected on rx
+#define PHY_INT_SSD             0x0800  // 1=No Start Of Stream detected on rx
+#define PHY_INT_ESD             0x0400  // 1=No End Of Stream detected on rx
+#define PHY_INT_RPOL            0x0200  // 1=Reverse Polarity detected
+#define PHY_INT_JAB             0x0100  // 1=Jabber detected
+#define PHY_INT_SPDDET          0x0080  // 1=100Base-TX mode, 0=10Base-T mode
+#define PHY_INT_DPLXDET         0x0040  // 1=Device in Full Duplex
+
+// PHY Interrupt/Status Mask Register
+#define PHY_MASK_REG            0x13    // Interrupt Mask
+// Uses the same bit definitions as PHY_INT_REG
+
+
 /*-------------------------------------------------------------------------
  *  I define some macros to make it easier to do somewhat common
  * or slightly complicated, repeated tasks.
diff --git a/src/drivers/net/sundance.c b/src/drivers/net/sundance.c
index 05621d4f2..701f922a4 100644
--- a/src/drivers/net/sundance.c
+++ b/src/drivers/net/sundance.c
@@ -52,13 +52,6 @@
 #define drv_version "v1.12"
 #define drv_date "2004-03-21"
 
-typedef unsigned char u8;
-typedef signed char s8;
-typedef unsigned short u16;
-typedef signed short s16;
-typedef unsigned int u32;
-typedef signed int s32;
-
 #define HZ 100
 
 /* Condensed operations for readability. */
diff --git a/src/drivers/net/tg3.c b/src/drivers/net/tg3.c
index 2d881f08a..ace2dfec6 100644
--- a/src/drivers/net/tg3.c
+++ b/src/drivers/net/tg3.c
@@ -9,6 +9,7 @@
 /* 11-13-2003	timlegge	Fix Issue with NetGear GA302T 
  * 11-18-2003   ebiederm        Generalize NetGear Fix to what the code was supposed to be.
  * 01-06-2005   Alf (Frederic Olivie) Add Dell bcm 5751 (0x1677) support
+ * 04-15-2005   Martin Vogt Add Fujitsu Siemens Computer (FSC) 0x1734 bcm 5751 0x105d support
  */
 
 #include "etherboot.h"
@@ -2413,6 +2414,9 @@ static struct subsys_tbl_ent subsys_id_to_phy_id[] = {
 	{ PCI_VENDOR_ID_DELL, 0x0109, PHY_ID_BCM5411 }, /* MERLOT */
 	{ PCI_VENDOR_ID_DELL, 0x010a, PHY_ID_BCM5411 }, /* SLIM_MERLOT */
 	{ PCI_VENDOR_ID_DELL, 0x0179, PHY_ID_BCM5751 }, /* EtherXpress */
+	
+	/* Fujitsu Siemens Computer */
+	{ PCI_VENDOR_ID_FSC, 0x105d, PHY_ID_BCM5751 }, /* Futro C200 */	
 
 	/* Compaq boards. */
 	{ PCI_VENDOR_ID_COMPAQ, 0x007c, PHY_ID_BCM5701 }, /* BANSHEE */
diff --git a/src/drivers/net/tg3.h b/src/drivers/net/tg3.h
index 6e05b9cc0..fd038f587 100644
--- a/src/drivers/net/tg3.h
+++ b/src/drivers/net/tg3.h
@@ -2156,7 +2156,7 @@ struct tg3 {
 	((X) == PHY_ID_BCM5400 || (X) == PHY_ID_BCM5401 || \
 	 (X) == PHY_ID_BCM5411 || (X) == PHY_ID_BCM5701 || \
 	 (X) == PHY_ID_BCM5703 || (X) == PHY_ID_BCM5704 || \
-	 (X) == PHY_ID_BCM5705 || (X) == PHY_ID_BCM5751 || \
+	 (X) == PHY_ID_BCM5705 || (X) == PHY_ID_BCM5750 || (X) == PHY_ID_BCM5751 || \
 	 (X) == PHY_ID_BCM8002 || (X) == PHY_ID_SERDES)
 
 	unsigned long			regs;
diff --git a/src/drivers/net/tlan.h b/src/drivers/net/tlan.h
index e0379a7bc..de57d5984 100644
--- a/src/drivers/net/tlan.h
+++ b/src/drivers/net/tlan.h
@@ -34,22 +34,10 @@
 * Indent Style: indent -kr -i8
 ***************************************************************************/
 
-/*
-#include <asm/io.h>
-#include <asm/types.h>
-#include <linux/netdevice.h>
-*/
-
-typedef unsigned char u8;
-typedef signed char s8;
-typedef unsigned short u16;
-typedef signed short s16;
-typedef unsigned int u32;
-typedef signed int s32;
-	/*****************************************************************
-	 * TLan Definitions
-	 *
-	 ****************************************************************/
+/*****************************************************************
+* TLan Definitions
+*
+****************************************************************/
 
 #define FALSE			0
 #define TRUE			1
diff --git a/src/drivers/net/tulip.c b/src/drivers/net/tulip.c
index 28e38d952..864e32af6 100644
--- a/src/drivers/net/tulip.c
+++ b/src/drivers/net/tulip.c
@@ -48,6 +48,8 @@
 /*********************************************************************/
 
 /*
+  08 Feb 2005  Ramesh Chander chhabaramesh at yahoo.co.in added table entries
+               for SGThomson STE10/100A
   07 Sep 2003  timlegge	Multicast Support Added
   11 Apr 2001  mdc     [patch to etherboot 4.7.24]
      Major rewrite to include Linux tulip driver media detection
@@ -118,13 +120,6 @@ static int tulip_debug = 2;             /* 1 normal messages, 0 quiet .. 7 verbo
 
 #define TX_TIME_OUT       2*TICKS_PER_SEC
 
-typedef uint8_t    u8;
-typedef  int8_t    s8;
-typedef uint16_t   u16;
-typedef  int16_t   s16;
-typedef uint32_t   u32;
-typedef  int32_t   s32;
-
 /* helpful macros if on a big_endian machine for changing byte order.
    not strictly needed on Intel */
 #define get_unaligned(ptr) (*(ptr))
@@ -157,7 +152,7 @@ static const char * const medianame[32] = {
 enum tulip_chips {
     DC21040=0, DC21041=1, DC21140=2, DC21142=3, DC21143=3,
     LC82C168, MX98713, MX98715, MX98725, AX88141, AX88140, PNIC2, COMET,
-    COMPEX9881, I21145, XIRCOM
+    COMPEX9881, I21145, XIRCOM, SGThomson,	/*Ramesh Chander*/
 };
 
 enum pci_id_flags_bits {
@@ -233,6 +228,8 @@ static const struct pci_id_info pci_id_tbl[] = {
       TULIP_IOTYPE, 256, MX98715 },
     { "3Com 3cSOHO100B-TX (ADMtek Centuar)", { 0x930010b7, 0xffffffff, 0, 0, 0, 0 },
       TULIP_IOTYPE, TULIP_SIZE, COMET },
+    { "SG Thomson STE10/100A", { 0x2774104a, 0xffffffff, 0, 0, 0, 0 },
+      TULIP_IOTYPE, 256, COMET },	/*Ramesh Chander*/
     { 0, { 0, 0, 0, 0, 0, 0 }, 0, 0, 0 },
 };
 
@@ -268,6 +265,7 @@ static struct tulip_chip_table {
       | HAS_PWRDWN | HAS_NWAY },
     { "Xircom tulip work-alike", HAS_MII | HAS_MEDIA_TABLE | ALWAYS_CHECK_MII 
       | HAS_PWRDWN | HAS_NWAY },
+    { "SGThomson STE10/100A", HAS_MII | MC_HASH_ONLY },	/*Ramesh Chander*/   
     { 0, 0 },
 };
 
@@ -1705,6 +1703,8 @@ static void init_media(struct nic *nic)
         outl(0x11000 | inw(ioaddr + 0xa0), ioaddr + 0xa0);
         break;
     case COMET:
+        /* Enable automatic Tx underrun recovery */
+        outl(inl(ioaddr + 0x88) | 1, ioaddr + 0x88);
         tp->if_port = 0;
 	tp->csr6 = 0x00040000;
         break;
@@ -2068,7 +2068,7 @@ PCI_ROM(0x125b, 0x1400, "ax88140",     "ASIX AX88140"),
 PCI_ROM(0x11f6, 0x9881, "rl100tx",     "Compex RL100-TX"),
 PCI_ROM(0x115d, 0x0003, "xircomtulip", "Xircom Tulip"),
 PCI_ROM(0x104a, 0x0981, "tulip-0981",  "Tulip 0x104a 0x0981"),
-PCI_ROM(0x104a, 0x2774, "tulip-2774",  "Tulip 0x104a 0x2774"),
+PCI_ROM(0x104a, 0x2774, "SGThomson-STE10100A", "Tulip 0x104a 0x2774"),	/*Modified by Ramesh Chander*/
 PCI_ROM(0x1113, 0x9511, "tulip-9511",  "Tulip 0x1113 0x9511"),
 PCI_ROM(0x1186, 0x1561, "tulip-1561",  "Tulip 0x1186 0x1561"),
 PCI_ROM(0x1259, 0xa120, "tulip-a120",  "Tulip 0x1259 0xa120"),
diff --git a/src/drivers/net/w89c840.c b/src/drivers/net/w89c840.c
index 1ed3503c8..c3f03f9f6 100644
--- a/src/drivers/net/w89c840.c
+++ b/src/drivers/net/w89c840.c
@@ -84,13 +84,6 @@
 
 static const char *w89c840_version = "driver Version 0.94 - December 12, 2003";
 
-typedef unsigned char  u8;
-typedef   signed char  s8;
-typedef unsigned short u16;
-typedef   signed short s16;
-typedef unsigned int   u32;
-typedef   signed int   s32;
-
 /* Linux support functions */
 #define virt_to_le32desc(addr)  virt_to_bus(addr)
 #define le32desc_to_virt(addr)  bus_to_virt(addr)