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* [build] Mark core files as permitted for UEFI Secure BootMichael Brown2026-01-1412-0/+12
| | | | | | | | | | | | Mark all files used in a standard build of bin-x86_64-efi/snponly.efi as permitted for UEFI Secure Boot. These files represent the core functionality of iPXE that is guaranteed to have been included in every binary that was previously subject to a security review and signed by Microsoft. It is therefore legitimate to assume that at least these files have already been reviewed to the required standard multiple times. Signed-off-by: Michael Brown <mcb30@ipxe.org>
* [pci] Allow probing permission to vary by rangeMichael Brown2025-11-252-2/+4
| | | | | | | Make pci_can_probe() part of the runtime selectable PCI I/O API, and defer this check to the per-range API. Signed-off-by: Michael Brown <mcb30@ipxe.org>
* [pci] Use linker tables for runtime selectable PCI APIsMichael Brown2025-11-243-32/+0Star
| | | | | | | Use the linker table mechanism to enumerate the underlying PCI I/O APIs, to allow PCIAPI_CLOUD to become architecture-independent code. Signed-off-by: Michael Brown <mcb30@ipxe.org>
* [bios] Use generic external heap based on the system memory mapMichael Brown2025-05-191-18/+0Star
| | | | Signed-off-by: Michael Brown <mcb30@ipxe.org>
* [bios] Describe umalloc() heap as an in-use memory areaMichael Brown2025-05-161-0/+1
| | | | | | | Use the concept of an in-use memory region defined as part of the system memory map API to describe the umalloc() heap. Signed-off-by: Michael Brown <mcb30@ipxe.org>
* [bios] Update to use the generic system memory map APIMichael Brown2025-05-161-0/+20
| | | | | | | | Provide an implementation of the system memory map API based on the assorted BIOS INT 15 calls, and a temporary implementation of the legacy get_memmap() function using the new API. Signed-off-by: Michael Brown <mcb30@ipxe.org>
* [acpi] Remove userptr_t from ACPI table parsingMichael Brown2025-04-221-2/+2
| | | | | | | Simplify the ACPI table parsing code by assuming that all table content is fully accessible via pointer dereferences. Signed-off-by: Michael Brown <mcb30@ipxe.org>
* [efi] Centralise definition of efi_cpu_nap()Michael Brown2024-09-131-18/+0Star
| | | | | | | | | Define a cpu_halt() function which is architecture-specific but platform-independent, and merge the multiple architecture-specific implementations of the EFI cpu_nap() function into a single central efi_cpu_nap() that uses cpu_halt() if applicable. Signed-off-by: Michael Brown <mcb30@ipxe.org>
* [pci] Separate permission to probe buses from bus:dev.fn range discoveryMichael Brown2024-08-153-0/+30
| | | | | | | | | | | | | | | | | The UEFI device model requires us to not probe the PCI bus directly, but instead to wait to be offered the opportunity to drive devices via our driver service binding handle. We currently inhibit PCI bus probing by having pci_discover() return an empty range when using the EFI PCI I/O API. This has the unwanted side effect that scanning the bus manually using the "pciscan" command will also fail to discover any devices. Separate out the concept of being allowed to probe PCI buses from the mechanism for discovering PCI bus:dev.fn address ranges, so that this limitation may be removed. Signed-off-by: Michael Brown <mcb30@ipxe.org>
* [cpuid] Allow reading hypervisor CPUID leavesMichael Brown2024-08-011-0/+3
| | | | | | | | | | | | | | Hypervisors typically intercept CPUID leaves in the range 0x40000000 to 0x400000ff, with leaf 0x40000000 returning the maximum supported function within this range in register %eax. iPXE currently masks off bit 30 from the requested CPUID leaf when checking to see if a function is supported, which causes this check to read from leaf 0x00000000 instead of 0x40000000. Fix by including bit 30 within the mask. Signed-off-by: Michael Brown <mcb30@ipxe.org>
* [ucode] Add support for updating x86 microcodeMichael Brown2024-03-151-0/+223
| | | | | | | | | | | | | | | | | | | Intel and AMD distribute microcode updates, which are typically applied by the BIOS and/or the booted operating system. BIOS updates can be difficult to obtain and cumbersome to apply, and are often neglected. Operating system updates may be subject to strict change control processes, particularly for production workloads. There is therefore value in being able to update the microcode at boot time using a freshly downloaded microcode update file, particularly in scenarios where the physical hardware and the installed operating system are controlled by different parties (such as in a public cloud infrastructure). Add support for parsing Intel and AMD microcode update images, and for applying the updates to all CPUs in the system. Signed-off-by: Michael Brown <mcb30@ipxe.org>
* [bios] Provide a multiprocessor API for BIOSMichael Brown2024-03-151-0/+32
| | | | | | | | Provide an implementation of the iPXE multiprocessor API for BIOS, based on sending broadcast INIT and SIPI interprocessor interrupts to start up all application processors. Signed-off-by: Michael Brown <mcb30@ipxe.org>
* [rng] Allow entropy source to be selected at runtimeMichael Brown2023-02-172-99/+0Star
| | | | | | | | | | | | | | | | | | | | | | | | As noted in commit 3c83843 ("[rng] Check for several functioning RTC interrupts"), experimentation shows that Hyper-V cannot be trusted to reliably generate RTC interrupts. (As noted in commit f3ba0fb ("[hyperv] Provide timer based on the 10MHz time reference count MSR"), Hyper-V appears to suffer from a general problem in reliably generating any legacy interrupts.) An alternative entropy source is therefore required for an image that may be used in a Hyper-V Gen1 virtual machine. The x86 RDRAND instruction provides a suitable alternative entropy source, but may not be supported by all CPUs. We must therefore allow for multiple entropy sources to be compiled in, with the single active entropy source selected only at runtime. Restructure the internal entropy API to allow a working entropy source to be detected and chosen at runtime. Enable the RDRAND entropy source for all x86 builds, since it is likely to be substantially faster than any other source. Signed-off-by: Michael Brown <mcb30@ipxe.org>
* [rng] Add RDRAND as an entropy sourceMichael Brown2023-02-152-0/+40
| | | | Signed-off-by: Michael Brown <mcb30@ipxe.org>
* [ioapi] Move PAGE_SHIFT to bits/io.hMichael Brown2023-02-061-3/+0Star
| | | | | | | | | | | The PAGE_SHIFT definition is an architectural property, rather than an aspect of a particular I/O API implementation (of which, in theory, there may be more than one per architecture). Reflect this by moving the definition to the top-level bits/io.h for each architecture. Signed-off-by: Michael Brown <mcb30@ipxe.org>
* [dhcp] Simplify platform-specific client architecture definitionsMichael Brown2023-01-221-0/+20
| | | | | | | | | | | | | | | | Move the platform-specific DHCP client architecture definitions to header files of the form <ipxe/$(PLATFORM)/dhcparch.h>. This simplifies the directory structure and allows the otherwise unused arch/$(ARCH)/include/$(PLATFORM) to be removed from the include directory search path, which avoids the confusing situation in which a header file may potentially be accessed through more than one path. For Linux userspace binaries on any architecture, use the EFI values for that architecture by delegating to the EFI header file. This avoids the need to explicitly select values for Linux userspace binaries for each architecture. Signed-off-by: Michael Brown <mcb30@ipxe.org>
* [pci] Select PCI I/O API at runtime for cloud imagesMichael Brown2022-09-183-0/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pretty much all physical machines and off-the-shelf virtual machines will provide a functional PCI BIOS. We therefore default to using only the PCI BIOS, with no fallback to an alternative mechanism if the PCI BIOS fails. AWS EC2 provides the opportunity to experience some exceptions to this rule. For example, the t3a.nano instances in eu-west-1 have no functional PCI BIOS at all. As of commit 83516ba ("[cloud] Use PCIAPI_DIRECT for cloud images") we therefore use direct Type 1 configuration space accesses in the images built and published for use in the cloud. Recent experience has discovered yet more variation in AWS EC2 instances. For example, some of the metal instance types have multiple PCI host bridges and the direct Type 1 accesses therefore see only a subset of the PCI devices. Attempt to accommodate future such variations by making the PCI I/O API selectable at runtime and choosing ECAM (if available), falling back to the PCI BIOS (if available), then finally falling back to direct Type 1 accesses. This is implemented as a dedicated PCIAPI_CLOUD API, rather than by having the PCI core select a suitable API at runtime (as was done for timers in commit 302f1ee ("[time] Allow timer to be selected at runtime"). The common case will remain that only the PCI BIOS API is required, and we would prefer to retain the optimisations that come from inlining the configuration space accesses in this common case. Cloud images are (at present) disk images rather than ROM images, and so the increased code size required for this design approach in the PCIAPI_CLOUD case is acceptable. Signed-off-by: Michael Brown <mcb30@ipxe.org>
* [pci] Generalise pci_num_bus() to pci_discover()Michael Brown2022-09-151-5/+9
| | | | | | | | | | Allow pci_find_next() to discover devices beyond the first PCI segment, by generalising pci_num_bus() (which implicitly assumes that there is only a single PCI segment) with pci_discover() (which has the ability to return an arbitrary contiguous chunk of PCI bus:dev.fn address space). Signed-off-by: Michael Brown <mcb30@ipxe.org>
* [rng] Check for TSC support before using RTC entropy sourceMichael Brown2021-05-121-0/+3
| | | | Signed-off-by: Michael Brown <mcb30@ipxe.org>
* [pci] Avoid scanning nonexistent buses when using PCIAPI_DIRECTMichael Brown2021-04-101-2/+2
| | | | | | | | | | | | | | There is no method for obtaining the number of PCI buses when using PCIAPI_DIRECT, and we therefore currently scan all possible bus numbers. This can cause a several-second startup delay in some virtualised environments, since PCI configuration space access will necessarily require the involvement of the hypervisor. Ameliorate this situation by defaulting to scanning only a single bus, and expanding the number of PCI buses to accommodate any subordinate buses that are detected during enumeration. Signed-off-by: Michael Brown <mcb30@ipxe.org>
* [acpi] Allow for platforms that provide ACPI tables individuallyMichael Brown2021-03-011-0/+13
| | | | | | | | | | | | | | | | The ACPI API currently expects platforms to provide access to a single contiguous ACPI table. Some platforms (e.g. Linux userspace) do not provide a convenient way to obtain the entire ACPI table, but do provide access to individual tables. All iPXE consumers of the ACPI API require access only to individual tables. Redefine the internal API to make acpi_find() an API method, with all existing implementations delegating to the current RSDT-based implementation. Signed-off-by: Michael Brown <mcb30@ipxe.org>
* [librm] Test for FXSAVE/FXRSTOR instruction supportMichael Brown2021-02-181-0/+3
| | | | | | | | | | | | | | | | | Assume that preservation of the %xmm registers is unnecessary during installation of iPXE into memory, since this is an operation that by its nature substantially disrupts large portions of the system anyway (such as the E820 memory map). This assumption allows us to utilise the existing CPUID code to check that FXSAVE/FXRSTOR are supported. Test for support during the call to init_librm and store the flag for use during subsequent calls to virt_call. Reduce the scope of TIVOLI_VMM_WORKAROUND to affecting only the call to check_fxsr(), to reduce #ifdef pollution in the remaining code. Debugged-by: Johannes Heimansberg <git@jhe.dedyn.io> Signed-off-by: Michael Brown <mcb30@ipxe.org>
* [pci] Define pci_ioremap() for mapping PCI bus addressesMichael Brown2020-09-242-0/+26
| | | | | | | Define pci_ioremap() as a wrapper around ioremap() that could allow for a non-zero address translation offset. Signed-off-by: Michael Brown <mcb30@ipxe.org>
* [rng] Use fixed-point calculations for min-entropy quantitiesMichael Brown2018-03-201-2/+2
| | | | | | | | | | | | | | We currently perform various min-entropy calculations using build-time floating-point arithmetic. No floating-point code ends up in the final binary, since the results are eventually converted to integers and asserted to be compile-time constants. Though this mechanism is undoubtedly cute, it inhibits us from using "-mno-sse" to prevent the use of SSE registers by the compiler. Fix by using fixed-point arithmetic instead. Signed-off-by: Michael Brown <mcb30@ipxe.org>
* [cpuid] Allow input %ecx value to be specifiedMichael Brown2017-06-161-4/+5
| | | | | | | | | | | | | | | | | | | | For some CPUID leaves (e.g. %eax=0x00000004), the result depends on the input value of %ecx. Allow this subfunction number to be specified as a parameter to the cpuid() wrapper. The subfunction number is exposed via the ${cpuid/...} settings mechanism using the syntax ${cpuid/<subfunction>.0x40.<register>.<function>} e.g. ${cpuid/0.0x40.0.0x0000000b} ${cpuid/1.0x40.0.0x0000000b} to retrieve the CPU topology information. Signed-off-by: Michael Brown <mcb30@ipxe.org>
* [acpi] Make acpi_find_rsdt() a per-platform methodMichael Brown2017-05-231-0/+18
| | | | Signed-off-by: Michael Brown <mcb30@ipxe.org>
* [time] Allow timer to be selected at runtimeMichael Brown2017-01-263-83/+6Star
| | | | | | | | | | | | | | | | | | | | | | Allow the active timer (providing udelay() and currticks()) to be selected at runtime based on probing during the INIT_EARLY stage of initialisation. TICKS_PER_SEC is now a fixed compile-time constant for all builds, and is independent of the underlying clock tick rate. We choose the value 1024 to allow multiplications and divisions on seconds to be converted to bit shifts. TICKS_PER_MS is defined as 1, allowing multiplications and divisions on milliseconds to be omitted entirely. The 2% inaccuracy in this definition is negligible when using the standard BIOS timer (running at around 18.2Hz). TIMER_RDTSC now checks for a constant TSC before claiming to be a usable timer. (This timer can be tested in KVM via the command-line option "-cpu host,+invtsc".) Signed-off-by: Michael Brown <mcb30@ipxe.org>
* [cpuid] Provide cpuid_supported() to test for supported functionsMichael Brown2017-01-251-4/+4
| | | | Signed-off-by: Michael Brown <mcb30@ipxe.org>
* [acpi] Add support for ACPI power offMichael Brown2016-07-112-0/+28
| | | | Signed-off-by: Michael Brown <mcb30@ipxe.org>
* [int13] Allow default drive to be specified via "san-drive" settingMichael Brown2016-03-221-11/+0Star
| | | | | | | | | | | The DHCP option 175.189 has been defined (by us) since 2006 as containing the drive number to be used for a SAN boot, but has never been automatically used as such by iPXE. Use this option (if specified) to override the default SAN drive number. Signed-off-by: Michael Brown <mcb30@ipxe.org>
* [librm] Support ioremap() for addresses above 4GB in a 64-bit buildMichael Brown2016-02-261-0/+24
| | | | Signed-off-by: Michael Brown <mcb30@ipxe.org>
* [ioapi] Split ioremap() out to a separate IOMAP APIMichael Brown2016-02-261-16/+1Star
| | | | Signed-off-by: Michael Brown <mcb30@ipxe.org>
* [bios] Add bin-x86_64-pcbios build platformMichael Brown2016-02-1611-0/+589
| | | | | | | | | | | | | | Move most arch/i386 files to arch/x86, and adjust the contents of the Makefiles and the include/bits/*.h headers to reflect the new locations. This patch makes no substantive code changes, as can be seen using a rename-aware diff (e.g. "git show -M5"). This patch does not make the pcbios platform functional for x86_64; it merely allows it to compile without errors. Signed-off-by: Michael Brown <mcb30@ipxe.org>
* [vmware] Expose GuestRPC mechanism in 64-bit buildsMichael Brown2016-01-052-0/+149
| | | | | | | | | The GuestRPC mechanism (used for VMWARE_SETTINGS and CONSOLE_VMWARE) does not use any real-mode code and so can be exposed in both 64-bit and 32-bit builds. Reported-by: Matthew Helton <mwhelton@gmail.com> Signed-off-by: Michael Brown <mcb30@ipxe.org>
* [legal] Relicense files under GPL2_OR_LATER_OR_UBDLMichael Brown2015-03-026-6/+6
| | | | | | | Relicense files for which I am the sole author (as identified by util/relicense.pl). Signed-off-by: Michael Brown <mcb30@ipxe.org>
* [timer] Rewrite the 8254 Programmable Interval Timer supportMichael Brown2015-02-171-0/+81
| | | | | | | | The 8254 timer code (used to implement udelay()) has an unknown provenance. Rewrite this code to avoid potential licensing uncertainty. Signed-off-by: Michael Brown <mcb30@ipxe.org>
* [hyperv] Add support for Hyper-V hypervisorMichael Brown2014-12-181-0/+3
| | | | | | | Add support for detecting and communicating with the Hyper-V hypervisor. Signed-off-by: Michael Brown <mcb30@ipxe.org>
* [ioapi] Centralise notion of PAGE_SIZEMichael Brown2014-07-281-0/+3
| | | | Signed-off-by: Michael Brown <mcb30@ipxe.org>
* [ioapi] Fail ioremap() when attempting to map a zero bus addressMichael Brown2014-07-161-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | When a 32-bit iPXE binary is running on a system which allocates PCI memory BARs above 4GB, our PCI subsystem will return the base address for any such BARs as zero (with a warning message if DEBUG=pci is enabled). Currently, ioremap() will happily map an address pointing to the start of physical memory, providing no sensible indication of failure. Fix by always returning NULL if we are asked to ioremap() a zero bus address. With a totally flat memory model (e.g. under EFI), this provides an accurate failure indication since no PCI peripheral will be mapped to the zero bus address. With the librm memory model, there is the possibility of a spurious NULL return from ioremap() if the bus address happens to be equal to virt_offset. Under the current virtual memory map, the NULL virtual address will always be the start of .textdata, and so this problem cannot occur; a NULL return from ioremap() will always be an accurate failure indication. Debugged-by: Anton D. Kachalov <mouse@yandex-team.ru> Signed-off-by: Michael Brown <mcb30@ipxe.org>
* [settings] Expose CPUID instruction via settings mechanismMichael Brown2013-08-071-0/+25
| | | | | | | | | | | | | | | | | | | | | | | Allow CPUID values to be read using the syntax ${cpuid/<register>.<function>} For example, ${cpuid/2.0x80000001} will give the value of %ecx after calling CPUID with %eax=0x80000001. Values for <register> are encoded as %eax=0, %ebx=1, %ecx=2, %edx=3. The numeric encoding is more sophisticated than described above, allowing for settings such as the CPU model (obtained by calling CPUID with %eax=0x80000002-0x80000004 inclusive and concatenating the values returned in %eax:%ebx:%ecx:%edx). See the source code for details. The "cpuvendor" and "cpumodel" settings provide easy access to these more complex CPUID settings. This functionality is intended to complement the "cpuid" command, which allows for testing individual CPUID feature bits. Signed-off-by: Michael Brown <mcb30@ipxe.org>
* [ioapi] Generalise i386 raw I/O API to x86Michael Brown2012-07-171-0/+159
| | | | Signed-off-by: Michael Brown <mcb30@ipxe.org>
* [cmdline] Add "cpuid" commandMichael Brown2012-06-071-0/+53
| | | | | | | Allow x86 CPU feature flags (such as support for 64-bit mode) to be checked using the "cpuid" command. Signed-off-by: Michael Brown <mcb30@ipxe.org>
* [pci] Replace pci_max_bus() with pci_num_bus()Michael Brown2011-02-171-4/+4
| | | | Signed-off-by: Michael Brown <mcb30@ipxe.org>
* [build] Rename gPXE to iPXEMichael Brown2010-04-203-0/+294
Access to the gpxe.org and etherboot.org domains and associated resources has been revoked by the registrant of the domain. Work around this problem by renaming project from gPXE to iPXE, and updating URLs to match. Also update README, LOG and COPYRIGHTS to remove obsolete information. Signed-off-by: Michael Brown <mcb30@ipxe.org>
generated by cgit v1.2.3-55-g7522 (git 2.39.0) at 2026-03-05 20:19:42 +0100