| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | [dwuart] Read input clock frequency from the device tree | Michael Brown | 2025-06-23 | 1 | -0/+8 |
| | | | | | | | | | | | | | | The 16550 design includes a programmable 16-bit clock divider for an arbitrary input clock, requiring knowledge of the input clock frequency in order to calculate the divider value for a given baud rate. The 16550 UARTs in an x86 PC will always have a 1.8432 MHz input clock. Non-x86 systems may have other input clock frequencies. Define the input clock frequency as a property of a 16550 UART, and read the value from the device tree "clock-frequency" property. Signed-off-by: Michael Brown <mcb30@ipxe.org> | ||||
| * | [dwuart] Add "ns16550a" compatible device ID | Michael Brown | 2025-06-23 | 1 | -0/+1 |
| | | | | | Signed-off-by: Michael Brown <mcb30@ipxe.org> | ||||
| * | [dwuart] Add a basic driver for the Synopsys DesignWare UART | Michael Brown | 2025-06-22 | 1 | -0/+120 |
| Signed-off-by: Michael Brown <mcb30@ipxe.org> | |||||
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