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* [intel] Exclude time spent in hypervisor from profilingMichael Brown2014-05-061-0/+3
| | | | | | | | When profiling, exclude any time spent inside the hypervisor responding to our MMIO accesses. This substantially reduces the variance accumulated on many other profilers. Signed-off-by: Michael Brown <mcb30@ipxe.org>
* [intel] Push new RX descriptors in batchesMichael Brown2014-04-281-8/+13
| | | | | | | | | | | | Inside a virtual machine, writing the RX ring tail pointer may incur a substantial overhead of processing inside the hypervisor. Minimise this overhead by writing the tail pointer once per batch of descriptors, rather than once per descriptor. Profiling under qemu-kvm (version 1.6.2) shows that this reduces the amount of time taken to refill the RX descriptor ring by around 90%. Signed-off-by: Michael Brown <mcb30@ipxe.org>
* [intel] Profile common virtual machine operationsMichael Brown2014-04-281-0/+19
| | | | | | | | | Operations which are negligible on physical hardware (such as issuing a posted write to the transmit ring tail register) may involve substantial amounts of processing within the hypervisor if running in a virtual machine. Signed-off-by: Michael Brown <mcb30@ipxe.org>
* [intel] Avoid completely filling the TX descriptor ringMichael Brown2014-04-222-1/+4
| | | | | | | | | | | | | It is unclear from the datasheets whether or not the TX ring can be completely filled (i.e. whether writing the tail value as equal to the current head value will cause the ring to be treated as completely full or completely empty). It is very plausible that this edge case could differ in behaviour between real hardware and the many implementations of an emulated Intel NIC found in various virtual machines. Err on the side of caution and always leave at least one ring entry empty. Signed-off-by: Michael Brown <mcb30@ipxe.org>
* [realtek] Clear bit 24 of RCRMichael Brown2014-03-202-2/+3
| | | | | | | | | | | | | | | | | | | | | | On an Asus Z87-K motherboard with an onboard 8168 NIC, booting into Windows 7 and then warm rebooting into iPXE results in a broken RX datapath: packets can be transmitted successfully but garbage is received. A cold reboot clears the problem. A dump of the PHY registers reveals only one difference: in the failure case the bits ADVERTISE_PAUSE_CAP and ADVERTISE_PAUSE_ASYM are cleared. Explicitly setting these bits does not fix the problem. A dump of the MAC registers reveals a few differences, of which the most obvious culprit is the undocumented bit 24 of the Receive Configuration Register (RCR), which is set in the failure case. Explicitly clearing this bit does fix the problem. Reported-by: Sebastian Nielsen <ipxe@sebbe.eu> Reported-by: Oliver Rath <rath@mglug.de> Debugged-by: Sebastian Nielsen <ipxe@sebbe.eu> Tested-by: Sebastian Nielsen <ipxe@sebbe.eu> Signed-off-by: Michael Brown <mcb30@ipxe.org>
* [realtek] Add ability to dump all internal registersMichael Brown2014-03-201-0/+27
| | | | Signed-off-by: Michael Brown <mcb30@ipxe.org>
* [realtek] Dump all MII register contents when link status changesMichael Brown2014-03-101-0/+1
| | | | Signed-off-by: Michael Brown <mcb30@ipxe.org>
* [realtek] Include link status register details in debug messagesMichael Brown2014-03-042-2/+39
| | | | Signed-off-by: Michael Brown <mcb30@ipxe.org>
* [intel] Add some missing PCI IDsMichael Brown2014-01-291-0/+2
| | | | | Tested-by: Philipp Hagen <Philipp.Hagen@she.net> Signed-off-by: Michael Brown <mcb30@ipxe.org>
* [settings] Explicitly separate the concept of a completed fetched settingMichael Brown2013-12-053-11/+14
| | | | | | | | | | The fetch_setting() family of functions may currently modify the definition of the specified setting (e.g. to add missing type information). Clean up this interface by requiring callers to provide an explicit buffer to contain the completed definition of the fetched setting, if required. Signed-off-by: Michael Brown <mcb30@ipxe.org>
* [intel] Add Intel I217 Gigabit Ethernet PCI IDlolipop2013-10-231-0/+1
| | | | Signed-off-by: Michael Brown <mcb30@ipxe.org>
* [linux] Apply MAC address prior to registering network deviceMichael Brown2013-09-031-5/+6
| | | | Signed-off-by: Michael Brown <mcb30@ipxe.org>
* [netdevice] Add method for generating EUI-64 address from link-layer addressMichael Brown2013-09-031-0/+1
| | | | Signed-off-by: Michael Brown <mcb30@ipxe.org>
* [linux] Give tap devices a name and bus typeMichael Brown2013-08-271-0/+3
| | | | | | | | Give tap devices a meaningful name, and avoid segmentation faults when attempting to retrieve ${net0/bustype} by assigning a new bus type for tap devices. Signed-off-by: Michael Brown <mcb30@ipxe.org>
* [3c90x] Fix High-MTU packet receptionThomas Miletich2013-08-201-0/+4
| | | | | | | | | | Prevent the card from flagging packets of 1518 bytes length as overlength. This fixes the High-MTU loopback test. Signed-off-by: Thomas Miletich <thomas.miletich@gmail.com> Signed-off-by: Michael Brown <mcb30@ipxe.org>
* [3c90x] Don't round up transmit packet lengthThomas Miletich2013-08-202-3/+5
| | | | | | | | | | The 3c90x B and C revisions support rounding up the packet length to a specific boundary. Disable this feature to avoid overlength packets. This fixes the loopback test. Signed-off-by: Thomas Miletich <thomas.miletich@gmail.com> Signed-off-by: Michael Brown <mcb30@ipxe.org>
* [3c90x] Stall upload engine before setting RX ring addressThomas Miletich2013-08-201-0/+4
| | | | | | | | According to the 3c90x datasheet we have to stall the upload (receive) engine before setting the receive ring address. Signed-off-by: Thomas Miletich <thomas.miletich@gmail.com> Signed-off-by: Michael Brown <mcb30@ipxe.org>
* [pci] Add pci_find_next() to iterate over existent PCI devicesMichael Brown2013-08-051-21/+44
| | | | Signed-off-by: Michael Brown <mcb30@ipxe.org>
* [legal] Add missing FILE_LICENCE declarationsMarin Hannache2013-07-157-0/+14
| | | | | Signed-off-by: Marin Hannache <git@mareo.fr> Signed-off-by: Michael Brown <mcb30@ipxe.org>
* [realtek] Allow extra space in RX buffersMichael Brown2013-07-151-1/+2
| | | | | | | | | | | Some hardware (observed with an onboard RTL8168) will erroneously report a buffer overflow error if the received packet exactly fills the receive buffer. Fix by adding an extra four bytes of padding to each receive buffer. Debugged-by: Thomas Miletich <thomas.miletich@gmail.com> Signed-off-by: Michael Brown <mcb30@ipxe.org>
* [velocity] Rewrite VIA Velocity driverAdrian Jamróz2013-07-154-3859/+1163Star
| | | | | | | Signed-off-by: Adrian Jamróz <adrian.jamroz@gmail.com> Modified-by: Thomas Miletich <thomas.miletich@gmail.com> Signed-off-by: Thomas Miletich <thomas.miletich@gmail.com> Signed-off-by: Michael Brown <mcb30@ipxe.org>
* [realtek] Report RX error detail in debug messagesMichael Brown2013-07-151-3/+5
| | | | Signed-off-by: Michael Brown <mcb30@ipxe.org>
* [legal] Add FILE_LICENCE for ath9k driver headersMarin Hannache2013-07-1413-0/+26
| | | | | | Signed-off-by: Marin Hannache <git@mareo.fr> Modified-by: Michael Brown <mcb30@ipxe.org> Signed-off-by: Michael Brown <mcb30@ipxe.org>
* [intel] Incorporate ring producer and consumer counters in diagnosticsMichael Brown2013-07-141-1/+6
| | | | Signed-off-by: Michael Brown <mcb30@ipxe.org>
* [rhine] Rewrite VIA Rhine driverAdrian Jamróz2013-07-143-1447/+1037Star
| | | | | | | | | | | | | | | | | | | | | | | Replace the old via-rhine driver with a new version using the iPXE API. Includes fixes by Thomas Miletich for: - MMIO access - Link detection - RX completion in RX overflow case - Reset and EEPROM reloading - CRC stripping - Missing cpu_to_le32() calls - Missing memory barriers Signed-off-by: Adrian Jamróz <adrian.jamroz@gmail.com> Modified-by: Thomas Miletich <thomas.miletich@gmail.com> Tested-by: Thomas Miletich <thomas.miletich@gmail.com> Tested-by: Robin Smidsrød <robin@smidsrod.no> Modified-by: Michael Brown <mcb30@ipxe.org> Tested-by: Michael Brown <mcb30@ipxe.org> Signed-off-by: Michael Brown <mcb30@ipxe.org>
* [settings] Expose PCI configuration space via settings mechanismMichael Brown2013-07-131-0/+124
| | | | | | | | | | | | | | | | Allow values to be read from PCI configuration space using the syntax ${pci/<busdevfn>.<offset>.<length>} where <busdevfn> is the bus:dev.fn address of the PCI device (expressed as a single integer, as returned by ${net0/busloc}), <offset> is the offset within PCI configuration space, and <length> is the length within PCI configuration space. Values are returned in reverse byte order, since PCI configuration space is little-endian by definition. Signed-off-by: Michael Brown <mcb30@ipxe.org>
* [realtek] Fix reopening of legacy-mode 8139 NICMichael Brown2013-05-261-3/+5
| | | | | | | | | | | | | | | realtek_destroy_ring() currently does nothing if the card is operating in legacy (pre-RTL8139C+) mode. In particular, the producer and consumer counters are incorrectly left holding their current values. Virtual hardware (e.g. the emulated RTL8139 in qemu and similar VMs) is tolerant of this behaviour, but real hardware will fail to transmit if the descriptors are not used in the correct order. Fix by resetting the producer and consumer counters in realtek_destroy_ring() even if the card is operating in legacy mode. Reported-by: Gelip <mrgelip@gmail.com> Signed-off-by: Michael Brown <mcb30@ipxe.org>
* [settings] Eliminate settings "tag magic"Michael Brown2013-05-011-8/+5Star
| | | | | | | Create an explicit concept of "settings scope" and eliminate the magic values used for numerical setting tags. Signed-off-by: Michael Brown <mcb30@ipxe.org>
* [realtek] Defer packets when no transmit descriptors are availableMichael Brown2013-05-011-3/+3
| | | | Signed-off-by: Michael Brown <mcb30@ipxe.org>
* [realtek] Ensure EEPROM writes reach chip before starting udelay()Michael Brown2013-05-011-0/+3
| | | | | | | | | | | | | | | On some systems, it appears to be possible for writes to the EEPROM registers to be delayed for long enough that the EEPROM's setup and hold times are violated, resulting in invalid data being read from the EEPROM. Fix by inserting a PCI read cycle immediately after writes to RTL_9346CR, to ensure that the write has completed before starting the udelay() used to time the SPI bus transitions. Reported-by: Gelip <mrgelip@gmail.com> Tested-by: Gelip <mrgelip@gmail.com> Signed-off-by: Michael Brown <mcb30@ipxe.org>
* [realtek] Allow reaction time between writing RTL_CAPR and reading RTL_CRMichael Brown2013-04-301-0/+3
| | | | | | | | | | | | | | Some older RTL8139 chips seem to not immediately update the RTL_CR.BUFE bit in response to a write to RTL_CAPR. This results in iPXE seeing a spurious zero-length received packet, and thereafter being out of sync with the hardware's RX ring offset. Fix by inserting an extra PCI read cycle after writing to RTL_CAPR, to give the chip time to react before we next read RTL_CR. Reported-by: Gelip <mrgelip@gmail.com> Tested-by: Gelip <mrgelip@gmail.com> Signed-off-by: Michael Brown <mcb30@ipxe.org>
* [realtek] Use ID word to detect EEPROM presenceMichael Brown2013-04-282-16/+42
| | | | | | | | | | | | | | | | | Some onboard RTL8169 NICs seem to leave the EEPROM pins disconnected. The existing is_valid_ether_addr() test will not necessarily catch this, since it expects a missing EEPROM to show up as a MAC address of 00:00:00:00:00:00 or ff:ff:ff:ff:ff:ff. When the EEPROM pins are floating the MAC address may read as e.g. 00:00:00:00:0f:00, which will not be detected as invalid. Check the ID word in the first two bytes of the EEPROM (which should have the value 0x8129 for all RTL8139 and RTL8169 chips), and use this to determine whether or not an EEPROM is present. Reported-by: Carl Karsten <carl@nextdayvideo.com> Tested-by: Carl Karsten <carl@nextdayvideo.com> Signed-off-by: Michael Brown <mcb30@ipxe.org>
* [build] Fix dubious uses of bitwise operatorsMichael Brown2013-04-281-1/+1
| | | | | | Detected by sparse. Signed-off-by: Michael Brown <mcb30@ipxe.org>
* [build] Fix uses of literal 0 as a NULL pointerMichael Brown2013-04-2810-19/+15Star
| | | | | | Detected using sparse. Signed-off-by: Michael Brown <mcb30@ipxe.org>
* [realtek] Print bad MAC address in debug message when inferring no EEPROMMichael Brown2013-04-271-1/+2
| | | | Signed-off-by: Michael Brown <mcb30@ipxe.org>
* [efi] Perform meaningful error code conversionsMichael Brown2013-04-191-38/+45
| | | | | | | | Exploit the redefinition of iPXE error codes to include a "platform error code" to allow for meaningful conversion of EFI_STATUS values to iPXE errors and vice versa. Signed-off-by: Michael Brown <mcb30@ipxe.org>
* [libc] Use __einfo() tuple as first argument to EUNIQ()Michael Brown2013-04-192-2/+2
| | | | Signed-off-by: Michael Brown <mcb30@ipxe.org>
* [intel] Add intelx driver for Intel 10 Gigabit Ethernet NICsMichael Brown2013-04-192-0/+579
| | | | Signed-off-by: Michael Brown <mcb30@ipxe.org>
* [intel] Expose functionality to be shared with intelx driverMichael Brown2013-04-192-15/+33
| | | | | | | | The Intel 10 Gigabit NICs have a datapath that is almost register-compatible with the Intel 1 Gigabit NICs. Expose common functionality to avoid duplication of code in the new "intelx" driver. Signed-off-by: Michael Brown <mcb30@ipxe.org>
* [intel] Remove hardcoded offsets for descriptor ring registersMichael Brown2013-04-192-18/+6Star
| | | | | | | | | | | | | | The Intel 10 Gigabit NICs use the same simplified (aka "legacy") descriptor format and the same layout for descriptor register blocks as the Intel 1 Gigabit NICs. The offsets of the descriptor register blocks are not the same. Simplify reuse of the existing code by removing all hardcoded offsets for registers within descriptor register blocks, and ensuring that all offsets are calculated using the descriptor register block base address provided via intel_init_ring(). Signed-off-by: Michael Brown <mcb30@ipxe.org>
* [prism2] Use standard type namesMichael Brown2013-03-274-1383/+1361Star
| | | | | | | | | | | Avoid using UINT16 and similar typedefs, which are non-standard in the iPXE codebase and generate conflicts when trying to include any of the EFI headers. Also fix trailing whitespace in the affected files, to prevent complaints from git. Signed-off-by: Michael Brown <mcb30@ipxe.org>
* [igbvf] Remove conflicting macro definitionsMichael Brown2013-03-251-3/+0Star
| | | | | | | Remove macros which aren't used anywhere in the driver, and which conflict with macros of the same name used in the EFI headers. Signed-off-by: Michael Brown <mcb30@ipxe.org>
* [cs89x0] Remove conflicting macro definitionsMichael Brown2013-03-251-3/+0Star
| | | | | | | Remove macros which aren't used anywhere in the driver, and which conflict with macros of the same name used in the EFI headers. Signed-off-by: Michael Brown <mcb30@ipxe.org>
* [tg3] Fix various tg3 issuesKevin Tran2013-03-042-1/+15
| | | | | Modified-by: Michael Brown <mcb30@ipxe.org> Signed-off-by: Michael Brown <mcb30@ipxe.org>
* [iscsi] Include 802.1Q VLAN identifier in iBFTStefan Hajnoczi2013-03-011-0/+3
| | | | | | | | | | | | | | | The iBFT NIC section has a VLAN field which must be filled in so that iSCSI booting works over VLANs. Unfortunately it is unclear from the IBM specification linked in ibft.c whether the VLAN field is just the 802.1Q VLAN Identifier or the full 802.1Q TCI. For now just fill in the VID, the Priority Code Point and Drop Eligible Indicator could be set in the future if it turns out they should be present too. Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com> Modified-by: Michael Brown <mcb30@ipxe.org> Signed-off-by: Michael Brown <mcb30@ipxe.org>
* [intel] Add Intel I210 Gigabit Ethernet PCI IDJens Rottmann2013-02-201-0/+1
| | | | | Signed-off-by: Jens Rottmann <JRottmann@LiPPERTembedded.de> Signed-off-by: Michael Brown <mcb30@ipxe.org>
* [src] Fix spelling in comments, debug messages and local variable namesStefan Weil2013-01-0328-63/+63
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fixes in comments and debug messages: existance -> existence unecessary -> unnecessary occured -> occurred decriptor -> descriptor neccessary -> necessary addres, adress -> address initilize -> initialize sucessfully -> successfully paramter -> parameter acess -> access upto -> up to likelyhood ->likelihood thru -> through substracting -> subtracting lenght -> length isnt -> isn't interupt -> interrupt publically -> publicly (this one was not wrong, but unusual) recieve -> receive accessable -> accessible seperately -> separately pacet -> packet controled -> controlled dectect -> detect indicies -> indices extremly -> extremely boundry -> boundary usefull -> useful unuseable -> unusable auxilliary -> auxiliary embeded -> embedded enviroment -> environment sturcture -> structure complier -> compiler constructes -> constructs supress -> suppress intruduced -> introduced compatability -> compatibility verfication -> verification ths -> the reponse -> response Fixes in local variable names: retreive -> retrieve Most of these fixes were made using codespell. Signed-off-by: Stefan Weil <sw@weilnetz.de> Modified-by: Michael Brown <mcb30@ipxe.org> Signed-off-by: Michael Brown <mcb30@ipxe.org>
* [forcedeth] Increase TX ring size to prevent dropped packetsMichael Brown2012-10-291-1/+1
| | | | | | | | | | | Commit 947976d ("[netdevice] Do not force a poll on net_tx()") requires network devices to have TX rings that are sufficiently large to allow a transmitted response to all packets received during a single poll. Reported-by: Robin Smidsrød <robin@smidsrod.no> Tested-by: Robin Smidsrød <robin@smidsrod.no> Signed-off-by: Michael Brown <mcb30@ipxe.org>
* [intel] Poll RX queue if hardware reports RX overflowMichael Brown2012-10-281-1/+1
| | | | | | | | | | | | | | | The Intel NIC emulation in some versions of VMware seems to suffer from a flaw whereby the Interrupt Cause Register (ICR) fails to assert the usual "packet received" bit (ICR.RXT0) if a receive overflow (ICR.RXO) has also occurred. Work around this flaw by polling for completed descriptors whenever either ICR.RXT0 or ICR.RXO is asserted. Reported-by: Miroslav Halas <miroslav.halas@bankofamerica.com> Debugged-by: Miroslav Halas <miroslav.halas@bankofamerica.com> Tested-by: Miroslav Halas <miroslav.halas@bankofamerica.com> Signed-off-by: Michael Brown <mcb30@ipxe.org>
* [hermon] Use PCI VPD for non-volatile option storageMichael Brown2012-10-252-2/+40
| | | | Signed-off-by: Michael Brown <mcb30@ipxe.org>
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