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* [build] Mark core files as permitted for UEFI Secure BootMichael Brown2026-01-144-0/+4
| | | | | | | | | | | | Mark all files used in a standard build of bin-x86_64-efi/snponly.efi as permitted for UEFI Secure Boot. These files represent the core functionality of iPXE that is guaranteed to have been included in every binary that was previously subject to a security review and signed by Microsoft. It is therefore legitimate to assume that at least these files have already been reviewed to the required standard multiple times. Signed-off-by: Michael Brown <mcb30@ipxe.org>
* [uart] Support 16550 UARTs accessed via either MMIO or port I/OMichael Brown2025-11-041-2/+2
| | | | | | | | | | | Use the combined accessors ioread8() and iowrite8() to read and write 16550 UART registers, to allow the decision between using MMIO and port I/O to be made at runtime. Minimise the increase in code size for x86 by ignoring the register shift, since this is essentially used only for non-x86 SoCs. Signed-off-by: Michael Brown <mcb30@ipxe.org>
* [riscv] Provide a DMA API implementation for RISC-V bare-metal systemsMichael Brown2025-07-091-0/+15
| | | | | | | | | Provide an implementation of dma_map() that performs cache clean or invalidation as required, and an implementation of dma_alloc() that returns virtual addresses within the coherent mapping of the 32-bit physical address space. Signed-off-by: Michael Brown <mcb30@ipxe.org>
* [uart] Add support for MMIO-accessible 16550 UARTsMichael Brown2025-06-201-4/+31
| | | | | | | | | | | | | | | | | 16550 UARTs exist on non-x86 platforms but will be accessible via MMIO rather than port I/O. It is possible to encounter MMIO-mapped 16550 UARTs on x86 platforms, but there is no real requirement to support them in iPXE since the standard COM1, COM2, etc ports have been present on every PC-compatible machine since 1981. Assume for now that accessing 16550 UART registers requires inb()/outb() on x86 and readb()/writeb() on other architectures. Allow for the existence of a register shift on MMIO-mapped 16550 UARTs, since modern SoCs tend to treat register addresses as being aligned to either 32-bit or 64-bit boundaries. Signed-off-by: Michael Brown <mcb30@ipxe.org>
* [uart] Allow for the existence of non-16550 UARTsMichael Brown2025-06-201-4/+4
| | | | | | | | | | | | | | | | | | | Remove the assumption that all platforms use a fixed number of 16550 UARTs identifiable by a simple numeric index. Create an abstraction allowing for dynamic instantiation and registration of any number of arbitrary UART models. The common case of the serial console on x86 uses a single fixed UART specified at compile time. Avoid unnecessarily dragging in the dynamic instantiation code in this use case by allowing COMCONSOLE to refer to a single static UART object representing the relevant port. When selecting a UART by command-line argument (as used in the "gdbstub serial <port>" command), allow the UART to be specified as either a numeric index (to retain backwards compatiblity) or a case-insensitive port name such as "COM2". Signed-off-by: Michael Brown <mcb30@ipxe.org>
* [lkrn] Add basic support for the RISC-V Linux kernel image formatMichael Brown2025-05-201-0/+17
| | | | | | | | | | | | | | | | | | | | | | The RISC-V and AArch64 bare-metal kernel images share a common header format, and require essentially the same execution environment: loaded close to the start of RAM, entered with paging disabled, and passed a pointer to a flattened device tree that describes the hardware and any boot arguments. Implement basic support for executing bare-metal RISC-V and AArch64 kernel images. The (trivial) AArch64-specific code path is untested since we do not yet have the ability to build for any bare-metal AArch64 platforms. Constructing and passing an initramfs image is not yet supported. Rename the IMAGE_BZIMAGE build configuration option to IMAGE_LKRN, since "bzImage" is specific to x86. To retain backwards compatibility with existing local build configurations, we leave IMAGE_BZIMAGE as the enabled option in config/default/pcbios.h and treat IMAGE_LKRN as a synonym for IMAGE_BZIMAGE when building for x86 BIOS. Signed-off-by: Michael Brown <mcb30@ipxe.org>
* [memmap] Define an API for managing the system memory mapMichael Brown2025-05-161-0/+15
| | | | | | | | | Define a generic system memory map API, based on the abstraction created for parsing the FDT memory map and adding a concept of hidden in-use memory regions as required to support patching the BIOS INT 15 memory map. Signed-off-by: Michael Brown <mcb30@ipxe.org>
* [riscv] Hold virtual address offset in the thread pointer registerMichael Brown2025-05-111-0/+15
| | | | | | | | | | | | iPXE does not make use of any thread-local storage. Use the otherwise unused thread pointer register ("tp") to hold the current value of the virtual address offset, rather than using a global variable. This ensures that virt_offset can be made valid even during very early initialisation (when iPXE may be executing directly from read-only memory and so cannot update a global variable). Signed-off-by: Michael Brown <mcb30@ipxe.org>
* [gdb] Allow CPU architectures to omit support for GDBMichael Brown2024-09-051-0/+45
| | | | | | | | Move the <gdbmach.h> file to <bits/gdbmach.h>, and provide a common dummy implementation for all architectures that have not yet implemented support for GDB. Signed-off-by: Michael Brown <mcb30@ipxe.org>
* [build] Centralise dummy architecture-specific headersMichael Brown2024-09-0315-0/+243
Simplify the process of adding a new CPU architecture by providing common implementations of typically empty architecture-specific header files. Signed-off-by: Michael Brown <mcb30@ipxe.org>