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| * [tls] Refuse to resume sessions with mismatched master secret methodsMichael Brown2025-10-131-0/+2
| | | | | | | | | | | | | | | | | | RFC 7627 section 5.3 states that the client must abort the handshake if the server attempts to resume a session where the master secret calculation method stored in the session does not match the method used for the connection being resumed. Signed-off-by: Michael Brown <mcb30@ipxe.org>
| * [tls] Add support for the Extended Master SecretMichael Brown2025-10-131-0/+5
| | | | | | | | | | | | | | | | | | | | | | RFC 7627 defines the Extended Master Secret (EMS) as an alternative calculation that uses the digest of all handshake messages rather than just the client and server random bytes. Add support for negotiating the Extended Master Secret extension and performing the relevant calculation of the master secret. Signed-off-by: Michael Brown <mcb30@ipxe.org>
| * [pci] Map all MSI-X interrupts to a dummy target address by defaultMichael Brown2025-10-091-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Interrupts as such are not used in iPXE, which operates in polling mode. However, some network cards (such as the Intel 40GbE and 100GbE NICs) will defer writing out completions until the point of asserting an MSI-X interrupt. From the point of view of the PCI device, asserting an MSI-X interrupt is just a 32-bit DMA write of an opaque value to an opaque target address. The PCI device has no know to know whether or not the target address corresponds to a real APIC. We can therefore trick the PCI device into believing that it is asserting an MSI-X interrupt, by configuring it to write an opaque 32-bit value to a dummy target address in host memory. This is sufficient to trigger the associated write of the completions to host memory. Allocate a dummy target address when enabling MSI-X on a PCI device, and map all interrupts to this target address by default. Signed-off-by: Michael Brown <mcb30@ipxe.org>
| * [efi] Add ability to extract device path from an EFI load optionMichael Brown2025-08-291-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | An EFI boot option (stored in a BootXXXX variable) comprises an EFI_LOAD_OPTION structure, which includes some undefined number of EFI device paths. (The structure is extremely messy and awkward to parse in C, but that's par for the course with EFI.) Add a function to extract the first device path from an EFI load option, along with wrapper functions to read and extract the first device path from an EFI boot variable. Signed-off-by: Michael Brown <mcb30@ipxe.org>
| * [libc] Add wcsnlen()Michael Brown2025-08-281-0/+1
| | | | | | | | Signed-off-by: Michael Brown <mcb30@ipxe.org>
| * [fdt] Provide fdt_reg() for unsized single-entry regionsMichael Brown2025-08-071-0/+3
| | | | | | | | | | | | | | | | Many region types (e.g. I2C bus addresses) can only ever contain a single region with no size cells specified. Provide fdt_reg() to reduce boilerplate in this common use case. Signed-off-by: Michael Brown <mcb30@ipxe.org>
| * [cmdline] Show commands in alphabetical orderMichael Brown2025-08-061-1/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | Commands were originally ordered by functional group (e.g. keeping the image management commands together), with arrays used to impose a functionally meaningful order within the group. As the number of commands and functional groups has expanded over the years, this has become essentially useless as an organising principle. Switch to sorting commands alphabetically (using the linker table mechanism). Signed-off-by: Michael Brown <mcb30@ipxe.org>
| * [digest] Add commands for all enabled digest algorithmsMichael Brown2025-08-061-0/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | Add "sha256sum", "sha512sum", and similar commands. Include these new commands only when DIGEST_CMD is enabled in config/general.h and the corresponding algorithm is enabled in config/crypto.h. Leave "mdsum" and "sha1sum" included whenever only DIGEST_CMD is enabled, to avoid potentially breaking backwards compatibility with builds that disabled MD5 or SHA-1 as a TLS or X.509 digest algorithm, but would still have expected those commands to be present. Signed-off-by: Michael Brown <mcb30@ipxe.org>
| * [dwgpio] Add driver for the DesignWare GPIO controllerMichael Brown2025-08-052-0/+13
| | | | | | | | Signed-off-by: Michael Brown <mcb30@ipxe.org>
| * [gpio] Add a framework for GPIO controllersMichael Brown2025-08-052-0/+200
| | | | | | | | Signed-off-by: Michael Brown <mcb30@ipxe.org>
| * [fdt] Use phandle as device locationMichael Brown2025-08-041-2/+1Star
| | | | | | | | | | | | | | | | | | | | | | | | | | Consumption of phandles will be in the form of locating a functional device (e.g. a GPIO device, or an I2C device, or a reset controller) by phandle, rather than locating the device tree node to which the phandle refers. Repurpose fdt_phandle() to obtain the phandle value (instead of searching by phandle), and record this value as the bus location within the generic device structure. Signed-off-by: Michael Brown <mcb30@ipxe.org>
| * [fdt] Add ability to locate node by phandleMichael Brown2025-07-221-0/+2
| | | | | | | | Signed-off-by: Michael Brown <mcb30@ipxe.org>
| * [dwusb] Add driver for DesignWare USB3 host controllerMichael Brown2025-07-211-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a basic driver for the DesignWare USB3 host controller as found in the Lichee Pi 4A. This driver covers only the DesignWare host controller hardware. On the Lichee Pi 4A, this is sufficient to get the single USB root hub port (exposed internally via the SODIMM connector) up and running. The driver does not yet handle the various GPIOs that control power and signal routing for the Lichee Pi 4A's onboard VL817 USB hub and the four physical USB-A ports. This therefore leaves the USB hub and the USB-A ports unpowered, and the USB2 root hub port routed to the physical USB-C port. Devices plugged in to the USB-A ports will not be powered up, and a device plugged in to the USB-C port will enumerate as a USB2 device. Signed-off-by: Michael Brown <mcb30@ipxe.org>
| * [xhci] Allow for non-PCI xHCI host controllersMichael Brown2025-07-211-0/+1184
| | | | | | | | | | | | | | Allow for the existence of xHCI host controllers where the underlying hardware is not a PCI device. Signed-off-by: Michael Brown <mcb30@ipxe.org>
| * [efi] Allow compiler to perform type checks on EFI_EVENTMichael Brown2025-07-151-4/+7
| | | | | | | | | | | | | | | | | | | | | | | | As with EFI_HANDLE, the EFI headers define EFI_EVENT as a void pointer, rendering EFI_EVENT compatible with a pointer to itself and hence guaranteeing that pointer type bugs will be introduced. Redefine EFI_EVENT as a pointer to an anonymous structure (as we already do for EFI_HANDLE) to allow the compiler to perform type checking as expected. Signed-off-by: Michael Brown <mcb30@ipxe.org>
| * [init] Show initialisation function names in debug messagesMichael Brown2025-07-151-0/+1
| | | | | | | | Signed-off-by: Michael Brown <mcb30@ipxe.org>
| * [efi] Drop to external TPL for calls to ConnectController()Michael Brown2025-07-142-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There is nothing in the current versions of the UEFI specification that limits the TPL at which we may call ConnectController() or DisconnectController(). However, at least some platforms (observed with a Lenovo ThinkPad T14s Gen 5) will occasionally and unpredictably lock up before returning from ConnectController() if called at a TPL higher than TPL_APPLICATION. Work around whatever defect is present on these systems by dropping to the current external TPL for all calls to ConnectController() or DisconnectController(). Signed-off-by: Michael Brown <mcb30@ipxe.org>
| * [efi] Provide efi_tpl_name() for transcribing TPLs in debug messagesMichael Brown2025-07-141-0/+2
| | | | | | | | Signed-off-by: Michael Brown <mcb30@ipxe.org>
| * [dwmac] Add driver for DesignWare Ethernet MACMichael Brown2025-07-101-0/+1
| | | | | | | | | | | | | | Add a basic driver for the DesignWare Ethernet MAC network interface as found in the Lichee Pi 4A. Signed-off-by: Michael Brown <mcb30@ipxe.org>
| * [riscv] Invalidate data cache on completed RX DMA buffersMichael Brown2025-07-102-4/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The data cache must be invalidated twice for RX DMA buffers: once before passing ownership to the DMA device (in case the cache happens to contain dirty data that will be written back at an undefined future point), and once after receiving ownership from the DMA device (in case the CPU happens to have speculatively accessed data in the buffer while it was owned by the hardware). Only the used portion of the buffer needs to be invalidated after completion, since we do not care about data within the unused portion. Update the DMA API to include the used length as an additional parameter to dma_unmap(), and add the necessary second cache invalidation pass to the RISC-V DMA API implementation. Signed-off-by: Michael Brown <mcb30@ipxe.org>
| * [riscv] Provide a DMA API implementation for RISC-V bare-metal systemsMichael Brown2025-07-092-0/+18
| | | | | | | | | | | | | | | | | | Provide an implementation of dma_map() that performs cache clean or invalidation as required, and an implementation of dma_alloc() that returns virtual addresses within the coherent mapping of the 32-bit physical address space. Signed-off-by: Michael Brown <mcb30@ipxe.org>
| * [dma] Use virtual addresses for dma_map()Michael Brown2025-07-082-31/+14Star
| | | | | | | | | | | | | | | | | | | | Cache management operations must generally be performed on virtual addresses rather than physical addresses. Change the address parameter in dma_map() to be a virtual address, and make dma() the API-level primitive instead of dma_phys(). Signed-off-by: Michael Brown <mcb30@ipxe.org>
| * [iobuf] Ensure I/O buffer data sits within unshared cachelinesMichael Brown2025-07-071-1/+5
| | | | | | | | | | | | | | | | | | | | | | On platforms where DMA devices are not in the same coherency domain as the CPU cache, we must ensure that DMA I/O buffers do not share cachelines with other data. Align the start and end of I/O buffers to IOB_ZLEN, which is larger than any cacheline size we expect to encounter. Signed-off-by: Michael Brown <mcb30@ipxe.org>
| * [uaccess] Allow for coherent DMA mapping of the 32-bit address spaceMichael Brown2025-07-041-7/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On platforms where DMA devices are not in the same coherency domain as the CPU cache, it is necessary to create page table entries where the translations are marked as uncacheable. We choose to place iPXE within the low 4GB of memory (since 32-bit DMA devices are still reasonably common even on systems with 64-bit CPUs). We therefore need to cover only the low 4GB of memory with these page table entries. Update virt_to_phys() to allow for the existence of such a mapping, assuming that iPXE itself will always reside within the top 4GB of the 64-bit virtual address space (and therefore that the DMA mapping must lie somewhere below this in the negative virtual address space). Signed-off-by: Michael Brown <mcb30@ipxe.org>
| * [legacy] Allocate legacy driver .bss-like segments at probe timeMichael Brown2025-06-242-29/+20Star
| | | | | | | | | | | | | | | | | | | | | | | | | | Some legacy drivers use large static allocations for transmit and receive buffers. To avoid bloating the .bss segment, we currently implement these as a single common symbol named "_shared_bss" (which is permissible since only one legacy driver may be active at any one time). Switch to dynamic allocation of these .bss-like segments, to avoid the requirement for using common symbols. Signed-off-by: Michael Brown <mcb30@ipxe.org>
| * [legacy] Rename the global legacy NIC to "legacy_nic"Michael Brown2025-06-241-3/+5
| | | | | | | | | | | | | | | | | | | | | | | | We currently have contexts in which the local variable "nic" is a pointer to the global variable also called "nic". This complicates the creation of macros. Rename the global variable to "legacy_nic" to reduce pollution of the global namespace and to allow for the creation of macros referring to fields within this global variable. Signed-off-by: Michael Brown <mcb30@ipxe.org>
| * [dwuart] Read input clock frequency from the device treeMichael Brown2025-06-231-3/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | The 16550 design includes a programmable 16-bit clock divider for an arbitrary input clock, requiring knowledge of the input clock frequency in order to calculate the divider value for a given baud rate. The 16550 UARTs in an x86 PC will always have a 1.8432 MHz input clock. Non-x86 systems may have other input clock frequencies. Define the input clock frequency as a property of a 16550 UART, and read the value from the device tree "clock-frequency" property. Signed-off-by: Michael Brown <mcb30@ipxe.org>
| * [serial] Allow platform to specify mechanism for identifying consoleMichael Brown2025-06-231-0/+54
| | | | | | | | | | | | | | | | | | Allow the platform configuration to provide a mechanism for identifying the serial console UART. Provide two globally available mechanisms: "null" (i.e. no serial console), and "fixed" (i.e. use whatever is specified by COMCONSOLE in config/serial.h). Signed-off-by: Michael Brown <mcb30@ipxe.org>
| * [dwuart] Add a basic driver for the Synopsys DesignWare UARTMichael Brown2025-06-221-0/+1
| | | | | | | | Signed-off-by: Michael Brown <mcb30@ipxe.org>
| * [uart] Allow for dynamically registered 16550 UARTsMichael Brown2025-06-221-2/+0Star
| | | | | | | | | | | | | | Use the generic UART driver-private data pointer, rather than embedding the generic UART within the 16550 UART structure. Signed-off-by: Michael Brown <mcb30@ipxe.org>
| * [uart] Add support for MMIO-accessible 16550 UARTsMichael Brown2025-06-202-4/+33
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 16550 UARTs exist on non-x86 platforms but will be accessible via MMIO rather than port I/O. It is possible to encounter MMIO-mapped 16550 UARTs on x86 platforms, but there is no real requirement to support them in iPXE since the standard COM1, COM2, etc ports have been present on every PC-compatible machine since 1981. Assume for now that accessing 16550 UART registers requires inb()/outb() on x86 and readb()/writeb() on other architectures. Allow for the existence of a register shift on MMIO-mapped 16550 UARTs, since modern SoCs tend to treat register addresses as being aligned to either 32-bit or 64-bit boundaries. Signed-off-by: Michael Brown <mcb30@ipxe.org>
| * [uart] Allow for the existence of non-16550 UARTsMichael Brown2025-06-206-90/+249
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Remove the assumption that all platforms use a fixed number of 16550 UARTs identifiable by a simple numeric index. Create an abstraction allowing for dynamic instantiation and registration of any number of arbitrary UART models. The common case of the serial console on x86 uses a single fixed UART specified at compile time. Avoid unnecessarily dragging in the dynamic instantiation code in this use case by allowing COMCONSOLE to refer to a single static UART object representing the relevant port. When selecting a UART by command-line argument (as used in the "gdbstub serial <port>" command), allow the UART to be specified as either a numeric index (to retain backwards compatiblity) or a case-insensitive port name such as "COM2". Signed-off-by: Michael Brown <mcb30@ipxe.org>
| * [uart] Remove ability to use frame formats other than 8n1Michael Brown2025-06-172-7/+2Star
| | | | | | | | | | | | | | | | | | | | In the context of serial consoles, the use of any frame formats other than the standard 8 data bits, no parity, and one stop bit is so rare as to be nonexistent. Remove the almost certainly unused support for custom frame formats. Signed-off-by: Michael Brown <mcb30@ipxe.org>
| * [dt] Allow for creation of standalone devicesMichael Brown2025-06-111-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We will want to be able to create the console device as early as possible. Refactor devicetree probing to remove the assumption that a devicetree device must have a devicetree parent, and expose functions to allow a standalone device to be created given only the offset of a node within the tree. The full device path is no longer trivial to construct with this assumption removed. The full path is currently used only for debug messages. Remove the stored full path, use just the node name for debug messages, and ensure that the topology information previously visible in the full path is reconstructible from the combined debug output if needed. Signed-off-by: Michael Brown <mcb30@ipxe.org>
| * [ipv4] Add support for classless static routesMichael Brown2025-06-102-0/+5
| | | | | | | | | | | | | | | | | | Add support for RFC 3442 classless static routes provided via DHCP option 121. Originally-implemented-by: Hazel Smith <hazel.smith@leicester.ac.uk> Originally-implemented-by: Raphael Pour <raphael.pour@hetzner.com> Signed-off-by: Michael Brown <mcb30@ipxe.org>
| * [ipv4] Extend routing mechanism to handle non-default routesMichael Brown2025-06-101-16/+61
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Extend the definition of an IPv4 routing table entry to allow for the expression of non-default gateways for specified off-link subnets, and of on-link secondary subnets (where we can send directly to the destination address even though our source address is not within the subnet). This more precise definition also allows us to correctly handle routing in the (uncommon for iPXE) case when multiple network interfaces are open concurrently and more than one interface has a default gateway. The common case of a single IPv4 address/netmask and a default gateway now results in two routing table entries. To retain backwards compatibility with existing documentation (and to avoid on-screen clutter), the "route" command prints default gateways on the same line as the locally assigned address. There is therefore no change in output from the "route" command unless explicit additional (off-link or on-link) routes are present. Signed-off-by: Michael Brown <mcb30@ipxe.org>
| * [ipv4] Add self-tests for IPv4 routingMichael Brown2025-06-101-0/+2
| | | | | | | | Signed-off-by: Michael Brown <mcb30@ipxe.org>
| * [dt] Locate parent node at point of use in dt_ioremap()Michael Brown2025-05-301-3/+0Star
| | | | | | | | | | | | | | | | | | | | | | | | We currently rely on the recursive nature of devicetree bus probing to obtain the region cell size specification from the parent device. This blocks the possibility of creating a standalone console device based on /chosen/stdout-path before probing the whole bus. Fix by using fdt_parent() to locate the parent device at the point of use within dt_ioremap(). Signed-off-by: Michael Brown <mcb30@ipxe.org>
| * [fdt] Provide ability to locate the parent device nodeMichael Brown2025-05-301-0/+2
| | | | | | | | Signed-off-by: Michael Brown <mcb30@ipxe.org>
| * [memmap] Allow explicit colour selection for memory map debug messagesMichael Brown2025-05-251-22/+25
| | | | | | | | | | | | | | | | | | | | | | Provide DBGC_MEMMAP() as a replacement for memmap_dump(), allowing the colour used to match other messages within the same message group. Retain a dedicated colour for output from memmap_dump_all(), on the basis that it is generally most useful to visually compare full memory dumps against previous full memory dumps. Signed-off-by: Michael Brown <mcb30@ipxe.org>
| * [memmap] Rename addr/last fields to min/max for clarityMichael Brown2025-05-232-25/+20Star
| | | | | | | | | | | | | | | | Use the terminology "min" and "max" for addresses covered by a memory region descriptor, since this is sufficiently intuitive to generally not require further explanation. Signed-off-by: Michael Brown <mcb30@ipxe.org>
| * [lkrn] Support initrd construction for RISC-V bare-metal kernelsMichael Brown2025-05-231-4/+2Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use the shared initrd reshuffling and CPIO header construction code for RISC-V bare-metal kernels. This allows for files to be injected into the constructed ("magic") initrd image in exactly the same way as is done for bzImage and UEFI kernels. We append a dummy image encompassing the FDT to the end of the reshuffle list, so that it ends up directly following the constructed initrd in memory (but excluded from the initrd length, which was recorded before constructing the FDT). We also temporarily prepend the kernel binary itself to the reshuffle list. This is guaranteed to be safe (since reshuffling is designed to be unable to fail), and avoids the requirement for the kernel segment to be available before reshuffling. This is useful since current RISC-V bare-metal kernels tend to be distributed as EFI zboot images, which require large temporary allocations from the external heap for the intermediate images created during archive extraction. Signed-off-by: Michael Brown <mcb30@ipxe.org>
| * [initrd] Split out initrd construction from bzimage.cMichael Brown2025-05-231-3/+16
| | | | | | | | | | | | | | | | | | Provide a reusable function initrd_load_all() to load all initrds (including any constructed CPIO headers) into a contiguous memory region, and support functions to find the constructed total length and permissible post-reshuffling load address range. Signed-off-by: Michael Brown <mcb30@ipxe.org>
| * [initrd] Rename bzimage_align() to initrd_align()Michael Brown2025-05-222-3/+15
| | | | | | | | | | | | | | Alignment of initrd lengths is applicable to all Linux kernels, not just those in the x86 bzImage format. Signed-off-by: Michael Brown <mcb30@ipxe.org>
| * [initrd] Swap initrds entirely in-place via triple reversalMichael Brown2025-05-221-6/+0Star
| | | | | | | | | | | | | | Eliminate the requirement for free space when reshuffling initrds by swapping adjacent initrds using an in-place triple reversal. Signed-off-by: Michael Brown <mcb30@ipxe.org>
| * [uheap] Expose external heap region directlyMichael Brown2025-05-222-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | We currently rely on implicit detection of the external heap region. The INT 15 memory map mangler relies on examining the corresponding in-use memory region, and the initrd reshuffler relies on performing a separate detection of the largest free memory block after startup has completed. Replace these with explicit public symbols to describe the external heap region. Signed-off-by: Michael Brown <mcb30@ipxe.org>
| * [lkrn] Allow a single initrd to be passed to the booted kernelMichael Brown2025-05-211-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | Allow a single initrd image to be passed verbatim to the booted RISC-V kernel, as a proof of concept. We do not yet support reshuffling to make optimal use of available memory, or dynamic construction of CPIO headers, but this is sufficient to allow iPXE to start up the Fedora 42 kernel with its matching initrd image. Signed-off-by: Michael Brown <mcb30@ipxe.org>
| * [fdt] Allow an initrd to be specified when creating a device treeMichael Brown2025-05-211-1/+2
| | | | | | | | | | | | | | Allow an initrd location to be specified in our constructed device tree via the "linux,initrd-start" and "linux,initrd-end" properties. Signed-off-by: Michael Brown <mcb30@ipxe.org>
| * [initrd] Move initrd reshuffling to be architecture-independent codeMichael Brown2025-05-212-0/+24
| | | | | | | | | | | | | | | | There is nothing x86-specific in initrd.c, and a variant of the reshuffling logic will be required for executing bare-metal kernels on RISC-V and AArch64. Signed-off-by: Michael Brown <mcb30@ipxe.org>
| * [lkrn] Add support for EFI zboot compressed kernel imagesMichael Brown2025-05-201-0/+34
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Current RISC-V and AArch64 kernels found in the wild tend not to be in the documented kernel format, but are instead "EFI zboot" kernels comprising a small EFI executable that decompresses and executes the inner payload (which is a kernel in the expected format). The EFI zboot header includes a recognisable magic value "zimg" along with two fields describing the offset and length of the compressed payload. We can therefore treat this as an archive image format, extracting the payload as-is and then relying on our existing ability to execute compressed images. This is sufficient to allow iPXE to execute the Fedora 42 RISC-V kernel binary as currently published. Signed-off-by: Michael Brown <mcb30@ipxe.org>
generated by cgit v1.2.3-55-g7522 (git 2.39.0) at 2026-03-09 15:39:00 +0100