[import] Import version 1.60

http://www.memtest.org/download/1.60/memtest86+-1.60.tar.gz

8 files changed, 83 insertions, 35 deletions

diff --git a/changelog b/changelog
index 9be4773..45fe88e 100644
--- a/changelog
+++ b/changelog
@@ -1,11 +1,20 @@
-Memtest86+ V1.55
+Memtest86+ V1.60
 
 Enhancements :
-- Added support for Intel E7221
-- Added support for nForce 4 Intel Edition
-- Added detection for ATi Radeon Xpress 200
-- Added ECC polling for Intel E7221
+	- Added Detection for Pentium D
+	- Added Detection for Athlon & Opteron Dual Core
+	- Added Detection for 90 nm Athlon 64 / Sempron
+	- Added Detection for 90 nm Opteron
+	- Added experimental detection for Intel E8500
+	- Added detection for VIA KT880
 
 Bug Fixes :
-- More precise detection of K8 Memory Freq.
-- Some minor bug fixes.
+	- Correct Venice core detected as 0.13 µm
+	- Correct AMD751 not detected since 1.55
+	- Correct i855/DDR333 detection bug
+	- Correct E7xxx ECC polling (thanks to S. Wangnick)
+	- Removed E7520 ECC Support (not reliable)
+	- Added BadRAM patch	
+	- Some minor bug fixes.
+
+---------------------------------
\ No newline at end of file
diff --git a/controller.c b/controller.c
index c17cef7..b98e105 100644
--- a/controller.c
+++ b/controller.c
@@ -405,6 +405,12 @@ static void setup_iE7xxx(void)
 		pci_conf_read(ctrl.bus, ctrl.dev, ctrl.fn, 0xE0, 2, &dvnp);
 		pci_conf_write(ctrl.bus, ctrl.dev, ctrl.fn , 0xE0, 2, (dvnp & 0xFE));
 
+		/* Clear any routing of ECC errors to interrupts that the BIOS might have set up */
+		pci_conf_write(ctrl.bus, ctrl.dev, ctrl.fn +1, 0x88, 1, 0x0);
+		pci_conf_write(ctrl.bus, ctrl.dev, ctrl.fn +1, 0x8A, 1, 0x0);
+		pci_conf_write(ctrl.bus, ctrl.dev, ctrl.fn +1, 0x8C, 1, 0x0);
+	
+
 	}
 
 	/* Clear any prexisting error reports */
@@ -1000,7 +1006,7 @@ static void poll_fsb_amd64(void) {
 		rdmsr(0xc0010015, mcgsrl, mcgsth);
 		fid = ((mcgsrl >> 24)& 0x3F);
 	}
-
+	
 	/* Extreme simplification. */
 	coef = ( fid / 2 ) + 4.0;
 
@@ -1310,7 +1316,7 @@ static void poll_fsb_i855(void) {
 	} else {
 		pci_conf_read( 0, 0, 0, 0xC6, 2, &mchcfg);
 		if (((mchcfg >> 10)&3) == 0) { dramratio = 1; }
-		else if (((mchcfg >> 10)&3) == 0) { dramratio = 1.666667; }
+		else if (((mchcfg >> 10)&3) == 1) { dramratio = 1.666667; }
 		else { dramratio = 1.333333333; }
 	}
 
@@ -1850,6 +1856,7 @@ static struct pci_memory_controller controllers[] = {
 	{ 0x1106, 0x0601, "VIA PLE133",  0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing },
 	{ 0x1106, 0x3099, "VIA KT266(A)/KT333", 0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing },
 	{ 0x1106, 0x3189, "VIA KT400(A)/600", 0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing },
+	{ 0x1106, 0x0269, "VIA KT880", 0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing },
 	{ 0x1106, 0x3205, "VIA KM400", 0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing },
 	{ 0x1106, 0x3116, "VIA KM266", 0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing },
 	{ 0x1106, 0x3156, "VIA KN266", 0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing },
@@ -1890,7 +1897,8 @@ static struct pci_memory_controller controllers[] = {
 	{ 0x8086, 0x255d, "Intel E7205",     0, poll_fsb_p4, poll_timings_nothing, setup_iE7xxx, poll_iE7xxx },
   { 0x8086, 0x3592, "Intel E7320",     0, poll_fsb_p4, poll_timings_E7520, setup_iE7520, poll_iE7520 },
   { 0x8086, 0x2588, "Intel E7221",     1, poll_fsb_i925, poll_timings_i925, setup_i925, poll_iE7221 },
-  { 0x8086, 0x3590, "Intel E7520",     0, poll_fsb_p4, poll_timings_E7520, setup_iE7520, poll_iE7520 },
+  { 0x8086, 0x3590, "Intel E7520",     0, poll_fsb_p4, poll_timings_E7520, setup_iE7520, poll_nothing },
+  { 0x8086, 0x2600, "Intel E8500",     0, poll_fsb_p4, poll_timings_nothing, setup_nothing, poll_nothing },
 	{ 0x8086, 0x2570, "Intel i848/i865", 0, poll_fsb_i875, poll_timings_i875, setup_i875, poll_nothing },
 	{ 0x8086, 0x2578, "Intel i875P",     0, poll_fsb_i875, poll_timings_i875, setup_i875, poll_i875 },
 	{ 0x8086, 0x2550, "Intel E7505",     0, poll_fsb_p4, poll_timings_nothing, setup_iE7xxx, poll_iE7xxx },
@@ -1991,7 +1999,7 @@ void find_controller(void)
 	result = pci_conf_read(ctrl.bus, ctrl.dev, ctrl.fn, PCI_DEVICE_ID, 2, &device);
 	ctrl.index = 0;	
 		if (result == 0) {
-			for(i = 2; i < sizeof(controllers)/sizeof(controllers[0]); i++) {
+			for(i = 1; i < sizeof(controllers)/sizeof(controllers[0]); i++) {
 				if ((controllers[i].vendor == vendor) && (controllers[i].device == device)) {
 					ctrl.index = i;
 					break;
diff --git a/init.c b/init.c
index 6f7d7ac..3b0c4c8 100644
--- a/init.c
+++ b/init.c
@@ -3,7 +3,7 @@
  * Released under version 2 of the Gnu Public License.
  * By Chris Brady, cbrady@sgi.com
  * ----------------------------------------------------
- * MemTest86+ V1.55 Specific code (GPL V2.0)
+ * MemTest86+ V1.60 Specific code (GPL V2.0)
  * By Samuel DEMEULEMEESTER, sdemeule@memtest.org
  * http://www.x86-secret.com - http://www.memtest.org
  */
@@ -52,7 +52,7 @@ static void display_init(void)
 	for(i=0, pp=(char *)(SCREEN_ADR+1); i<TITLE_WIDTH; i++, pp+=2) {
 		*pp = 0x20;
 	}
-	cprint(0, 0, "      Memtest86  v1.55      ");
+	cprint(0, 0, "      Memtest86  v1.60      ");
 
 	for(i=0, pp=(char *)(SCREEN_ADR+1); i<2; i++, pp+=30) {
 		*pp = 0xA4;
@@ -470,28 +470,41 @@ void cpu_type(void)
 			l2_cache += cpu_id.cache_info[10];
 			switch(cpu_id.model) {
 			default:
-				cprint(LINE_CPU, 0, "AMD Athlon 64");
-				off = 13;
+				cprint(LINE_CPU, 0, "AMD K8");
+				off = 6;
 				break;
+			case 1:
 			case 5:
-				cprint(LINE_CPU, 0, "AMD Opteron (0.13)");
-				off = 18;
-				break;
-			case  4:
-			case 12:
-				if (l2_cache == 256) {
-					cprint(LINE_CPU, 0, "AMD Sempron (0.13)");
-					off = 18;
+				if (((cpu_id.ext >> 16) & 0xF) != 0) {
+					cprint(LINE_CPU, 0, "AMD Opteron (0.09)");				
 				} else {
-					cprint(LINE_CPU, 0, "Athlon 64 (0.13)");
-					off = 16;
+					cprint(LINE_CPU, 0, "AMD Opteron (0.13)");
 				}
+				off = 18;
+				break;
+			case 3:
+			case 11:
+				cprint(LINE_CPU, 0, "Athlon 64 X2");
+				off = 12;				
 				break;
+			case 4:
+			case 7:
+			case 9:
+			case 12:
+			case 14:
 			case 15:
-				if ((cpu_id.ext >> 16) & 1) {
-				cprint(LINE_CPU, 0, "Athlon 64 (0.09)");
+				if (((cpu_id.ext >> 16) & 0xF) != 0) {
+					if (l2_cache > 256) {
+						cprint(LINE_CPU, 0, "Athlon 64 (0.09)");
+					} else {
+						cprint(LINE_CPU, 0, "Sempron (0.09)");						
+					}
 				} else {
-				cprint(LINE_CPU, 0, "Athlon 64 (0.13)");			
+					if (l2_cache > 256) {
+						cprint(LINE_CPU, 0, "Athlon 64 (0.13)");
+					} else {
+						cprint(LINE_CPU, 0, "Sempron (0.13)");						
+					}		
 				}
 				off = 16;
 				break;
@@ -727,8 +740,6 @@ void cpu_type(void)
 					}
 					break;
 				case 3:
-				case 4:
-				case 5:
 					if (l2_cache == 256) {
 						cprint(LINE_CPU, 0, "Celeron (0.09)");
 						off = 14;
@@ -743,6 +754,14 @@ void cpu_type(void)
 						off = 16;
 					}
 					break;
+				case 4:
+					cprint(LINE_CPU, 0, "Pentium D (0.09)");
+					off = 16;		
+					break;
+				default:
+					cprint(LINE_CPU, 0, "Unknown Intel");
+					off = 13;		
+					break;													
 				}
 				break;
 			}
diff --git a/mt86+_loader b/mt86+_loader
index f857642..c16a469 100644
--- a/mt86+_loader
+++ b/mt86+_loader
diff --git a/mt86+_loader.asm b/mt86+_loader.asm
index d678208..4711764 100644
--- a/mt86+_loader.asm
+++ b/mt86+_loader.asm
@@ -12,8 +12,8 @@
 ; The good thing is that you get a single file which can be
 ; compressed, for example with http://upx.sf.net/ (UPX).
 
-%define fullsize (99720 + buffer - exeh)
-	; 99720 is the size of memtest86+ V1.55, adjust as needed!
+%define fullsize (99784 + buffer - exeh)
+	; 99784 is the size of memtest86+ V1.60, adjust as needed!
 
 %define stacksize 2048
 %define stackpara ((stacksize + 15) / 16)
diff --git a/patn.c b/patn.c
index f5a2e75..0c5b490 100644
--- a/patn.c
+++ b/patn.c
@@ -6,6 +6,10 @@
  * Released under version 2 of the Gnu Public License.
  *
  * By Rick van Rein, vanrein@zonnet.nl
+ * ----------------------------------------------------
+ * MemTest86+ V1.60 Specific code (GPL V2.0)
+ * By Samuel DEMEULEMEESTER, sdemeule@memtest.org
+ * http://www.x86-secret.com - http://www.memtest.org 
  */
 
 
@@ -28,13 +32,15 @@
  *  - Print a new pattern only when the pattern array is changed.
  */
 
+#define COMBINE_MASK(a,b,c,d) ((a & b & c & d) | (~a & b & ~c & d))
 
 /* Combine two adr/mask pairs to one adr/mask pair.
  */
 void combine (ulong adr1, ulong mask1, ulong adr2, ulong mask2,
 		ulong *adr, ulong *mask) {
-	*mask = (adr1 & ~mask1 & adr2 & ~mask2) |
-			(adr1 & mask1 & adr2 & mask2);
+
+	*mask = COMBINE_MASK (adr1, mask1, adr2, mask2);
+
 	*adr  = adr1 | adr2;
 	*adr &= *mask;	// Normalise, no fundamental need for this
 }
diff --git a/precomp.bin b/precomp.bin
index 2cff4c5..b602352 100644
--- a/precomp.bin
+++ b/precomp.bin
diff --git a/test.c b/test.c
index fae2308..aedd8b9 100644
--- a/test.c
+++ b/test.c
@@ -4,7 +4,7 @@
  * Released under version 2 of the Gnu Public License.
  * By Chris Brady, cbrady@sgi.com
  * ----------------------------------------------------
- * MemTest86+ V2.00 Specific code (GPL V2.0)
+ * MemTest86+ V1.60 Specific code (GPL V2.0)
  * By Samuel DEMEULEMEESTER, sdemeule@memtest.org
  * http://www.x86-secret.com - http://www.memtest.org
  */
@@ -1466,6 +1466,12 @@ static void print_err_counts(void)
 	int i;
 	char *pp;
 
+	if ((v->ecount > 1048756) && (v->ecount % 32768 != 0))
+	    return;
+	   
+	if ((v->ecount > 2048) && (v->ecount % 1024 != 0))
+	    return;
+	  
 	dprint(LINE_INFO, COL_ERR, v->ecount, 6, 0);
 	dprint(LINE_INFO, COL_ECC_ERR, v->ecc_ecount, 6, 0);