[import] Import version 2.11

http://www.memtest.org/download/2.11/memtest86+-2.11.tar.gz

9 files changed, 80 insertions, 71 deletions

diff --git a/Makefile b/Makefile
index e8f0acf..bffb0d3 100644
--- a/Makefile
+++ b/Makefile
@@ -11,7 +11,7 @@ FDISK=/dev/fd0
 AS=as -32
 CC=gcc
 
-CFLAGS= -fno-stack-protector -Wall -march=i486 -m32 -Os -fomit-frame-pointer -fno-builtin -ffreestanding -fPIC
+CFLAGS= -Wall -march=i486 -m32 -Os -fomit-frame-pointer -fno-builtin -ffreestanding -fPIC
 
 OBJS= head.o reloc.o main.o test.o init.o lib.o patn.o screen_buffer.o \
       config.o linuxbios.o memsize.o pci.o controller.o random.o extra.o \
diff --git a/changelog b/changelog
index 297fecd..201df77 100644
--- a/changelog
+++ b/changelog
@@ -1,22 +1,10 @@
-Memtest86+ V2.10 changelog

+Memtest86+ V2.11 changelog

 --------------------------

 

-  - Added support for Intel Core i7 (Nehalem) CPU

- 	- Added support for Intel Atom Processors

- 	- Added support for Intel G41/G43/G45 Chipsets

- 	- Added support for Intel P43/P45 Chipsets

-	- Added support for Intel US15W (Poulsbo) Chipset

-  - Added support for Intel EP80579 (Tolapai) SoC CPU

-	- Added support for ICH10 Southbridge (SPD/DMI)

-	- Added detection for Intel 5000X

-  - Added workaround for DDR3 DMI detection

-  - Now fully aware of CPU w/ L3 cache (Core i7 & K10)

-	- Fixed Intel 5000Z chipset detection

-	- Fixed Memory Frequency on AMD K10

-	- Fixed cache detection on C7/Isaiah CPU

-  - Fix Memtest86+ not recognized as Linux Kernel

-

-Warning : GCC 4.2+ is not yet supported. Thanks to the new pointers over/underflows limitations 

-introduced with that version ! Memtest86+ compiled with GCC 4.2+ will result in a non-working 

-binary (hangs in the first seconds). We're working on a fix but there is really many parts of

-the code to check & change everywhere. So, please use GCC 4.1 instead.

+  - Added support for Intel Core i5 (Lynnfield) CPU

+  - Added support for Intel P55 Southbridge

+  - Added support for Intel PM45/GM45/GM47 Mobile chipset

+  - Added support for Intel GL40/GS45 Mobile chipset

+  - Corrected DDR2/DDR3 detection on Intel x35/x45

+  - Corrected detection on some Core i7 CPU 

+  - Various bug fixes

diff --git a/controller.c b/controller.c
index 4cb8831..f57618e 100644
--- a/controller.c
+++ b/controller.c
@@ -3,7 +3,7 @@
  * Released under version 2 of the Gnu Public License.
  * By Chris Brady, cbrady@sgi.com
  * ----------------------------------------------------
- * MemTest86+ V2.10 Specific code (GPL V2.0)
+ * MemTest86+ V2.11 Specific code (GPL V2.0)
  * By Samuel DEMEULEMEESTER, sdemeule@memtest.org
  * http://www.canardpc.com - http://www.memtest.org
  */
@@ -1593,6 +1593,7 @@ static void poll_fsb_im965(void) {
 		case 1: fsb_mch = 533; break;
 		default: case 2:	fsb_mch = 800; break;
 		case 3:	fsb_mch = 667; break;				
+		case 6:	fsb_mch = 1066; break;			
 	}
 
 
@@ -1614,7 +1615,6 @@ static void poll_fsb_im965(void) {
 			case 5:	dramratio = 12.0f/5.0f; break;
 		}
 		break;
-		
 	default:
 	case 800:
 		switch ((mchcfg >> 4)&7) {
@@ -1625,7 +1625,12 @@ static void poll_fsb_im965(void) {
 			case 5:	dramratio = 2.0f; break;
 		}
 		break;
-
+	case 1066:
+		switch ((mchcfg >> 4)&7) {
+			case 5:	dramratio = 3.0f/2.0f; break;
+			case 6:	dramratio = 2.0f; break;
+		}
+		break;
 }
 
 	// Compute RAM Frequency
@@ -2361,10 +2366,15 @@ static void poll_timings_im965(void) {
 static void poll_timings_p35(void) {
 
 	// Thanks for CDH optis
-	ulong dev0, temp, Memory_Check,	c0ckectrl, c1ckectrl, offset;
+	float cas;
+	int rcd, rp, ras;
+	ulong dev0, Device_ID, Memory_Check,	c0ckectrl, c1ckectrl, offset;
 	ulong ODT_Control_Register, Precharge_Register, ACT_Register, Read_Register, Misc_Register;
 	long *ptr;
 
+	pci_conf_read( 0, 0, 0, 0x02, 2, &Device_ID);
+	Device_ID &= 0xFFFF;
+
 	//Now, read MMR Base Address
 	pci_conf_read( 0, 0, 0, 0x48, 4, &dev0);
 	dev0 &= 0xFFFFC000;
@@ -2393,48 +2403,45 @@ static void poll_timings_p35(void) {
 	ptr = (long*)(dev0+offset+0x244);
 	Misc_Register = *ptr & 0xFFFFFFFF;
 
-	ptr = (long*)(dev0+offset+0x1E8);
-	Memory_Check = *ptr & 0xFFFFFFFF;	
+	// On P45, check 1A8
+	if(Device_ID > 0x2E00) {
+		ptr = (long*)(dev0+offset+0x1A8);
+		Memory_Check = *ptr & 0xFFFFFFFF;	
+		Memory_Check >>= 2;
+		Memory_Check &= 1;
+		Memory_Check = !Memory_Check;
+	} else {
+		ptr = (long*)(dev0+offset+0x1E8);
+		Memory_Check = *ptr & 0xFFFFFFFF;		
+	}
 
-	//Determine DDR or DDR-II
-	
+	//Determine DDR-II or DDR-III
 	if (Memory_Check & 1) {
 		cprint(LINE_CPU+5, col +1, "- Type : DDR2");
 	} else {
 		cprint(LINE_CPU+5, col +1, "- Type : DDR3");
 	}
 
-	// Now, detect timings
-	cprint(LINE_CPU+6, col2 +1, "/ CAS : ");
-	col2 += 9;
-
 	// CAS Latency (tCAS)
-	temp = ((ODT_Control_Register >> 8)& 0x3F) - 9.0f;
-	if (!(Memory_Check & 1)) { temp += 3.0f; }
-	dprint(LINE_CPU+6, col2, temp, 1 ,0);
-	cprint(LINE_CPU+6, col2+1, "-");
-	(temp < 10)?(col2 += 2):(col2 += 3);
+	if(Device_ID > 0x2E00) {
+		cas = ((ODT_Control_Register >> 8)& 0x3F) - 6.0f;
+	} else {
+		cas = ((ODT_Control_Register >> 8)& 0x3F) - 9.0f;
+	}
 
 	// RAS-To-CAS (tRCD)
-	temp = (Read_Register >> 17) & 0xF;
-	dprint(LINE_CPU+6, col2, temp, 1 ,0);
-	cprint(LINE_CPU+6, col2+1, "-");
-	(temp < 10)?(col2 += 2):(col2 += 3);
+	rcd = (Read_Register >> 17) & 0xF;
 
 	// RAS Precharge (tRP)
-	temp = (ACT_Register >> 13) & 0xF;
-	dprint(LINE_CPU+6, col2, temp, 1 ,0);
-	cprint(LINE_CPU+6, col2+1, "-");
-	(temp < 10)?(col2 += 2):(col2 += 3);
+	rp = (ACT_Register >> 13) & 0xF;
 
 	// RAS Active to precharge (tRAS)
-	temp = Precharge_Register & 0x3F;
-	dprint(LINE_CPU+6, col2, temp, 1 ,0);
-	(temp < 10)?(col2 += 1):(col2 += 2);
+	ras = Precharge_Register & 0x3F;
+	
+	print_timings_info(cas, rcd, rp, ras);
 
 	cprint(LINE_CPU+6, col2+1, "/"); col2 +=2;
 
-
 	if ((c0ckectrl >> 20 & 0xF) && (c1ckectrl >> 20 & 0xF)) { 
 		cprint(LINE_CPU+6, col2+1, "Dual Channel"); 
 	}	else {
@@ -3057,12 +3064,13 @@ static struct pci_memory_controller controllers[] = {
 	{ 0x8086, 0x29A0, "Intel P965/G965", 		0, poll_fsb_i965, poll_timings_i965, setup_p35, poll_nothing},
 	{ 0x8086, 0x2A00, "Intel GM965/GL960", 	0, poll_fsb_im965, poll_timings_im965, setup_p35, poll_nothing},
 	{ 0x8086, 0x2A10, "Intel GME965/GLE960",0, poll_fsb_im965, poll_timings_im965, setup_p35, poll_nothing},	
+	{ 0x8086, 0x2A40, "Intel PM/GM45/47",		0, poll_fsb_im965, poll_timings_im965, setup_p35, poll_nothing},	
 	{ 0x8086, 0x29B0, "Intel Q35", 	 		 		0, poll_fsb_i965, poll_timings_p35, setup_p35, poll_nothing},	
 	{ 0x8086, 0x29C0, "Intel P35/G33", 	 		0, poll_fsb_i965, poll_timings_p35, setup_p35, poll_nothing},	
 	{ 0x8086, 0x29D0, "Intel Q33",	  	 		0, poll_fsb_i965, poll_timings_p35, setup_p35, poll_nothing},	
 	{ 0x8086, 0x29E0, "Intel X38/X48", 	 		0, poll_fsb_i965, poll_timings_p35, setup_p35, poll_nothing},			
 	{ 0x8086, 0x2E10, "Intel Q45/Q43", 	 		0, poll_fsb_i965, poll_timings_p35, setup_p35, poll_nothing},	
-	{ 0x8086, 0x2E20, "Intel P45/G43",	  	0, poll_fsb_i965, poll_timings_p35, setup_p35, poll_nothing},	
+	{ 0x8086, 0x2E20, "Intel P45/G45",	  	0, poll_fsb_i965, poll_timings_p35, setup_p35, poll_nothing},	
 	{ 0x8086, 0x2E30, "Intel G41", 	 				0, poll_fsb_i965, poll_timings_p35, setup_p35, poll_nothing},	
 	{ 0x8086, 0x4001, "Intel 5400A", 		 		0, poll_fsb_5400, poll_timings_5400, setup_E5400, poll_nothing},		
 	{ 0x8086, 0x4003, "Intel 5400B", 		 		0, poll_fsb_5400, poll_timings_5400, setup_E5400, poll_nothing},		
@@ -3073,6 +3081,11 @@ static struct pci_memory_controller controllers[] = {
 	{ 0x8086, 0x5020, "Intel EP80579",    	0, poll_fsb_p4, 	poll_timings_EP80579, setup_nothing, poll_nothing },
 	{ 0x8086, 0x8100, "Intel US15W",				0, poll_fsb_us15w, poll_timings_us15w, setup_nothing, poll_nothing},
 	{ 0x8086, 0x8101, "Intel UL11L/US15L", 	0, poll_fsb_us15w, poll_timings_us15w, setup_nothing, poll_nothing},
+	{ 0x8086, 0x3400, "NHM IMC", 	 					0, poll_fsb_nhm, 	poll_timings_nhm, setup_nhm, poll_nothing},
+	{ 0x8086, 0x3401, "NHM IMC", 	 					0, poll_fsb_nhm, 	poll_timings_nhm, setup_nhm, poll_nothing},
+	{ 0x8086, 0x3402, "NHM IMC", 	 					0, poll_fsb_nhm, 	poll_timings_nhm, setup_nhm, poll_nothing},
+	{ 0x8086, 0x3403, "NHM IMC", 	 					0, poll_fsb_nhm, 	poll_timings_nhm, setup_nhm, poll_nothing},
+	{ 0x8086, 0x3404, "NHM IMC", 	 					0, poll_fsb_nhm, 	poll_timings_nhm, setup_nhm, poll_nothing},
 	{ 0x8086, 0x3405, "NHM IMC", 	 					0, poll_fsb_nhm, 	poll_timings_nhm, setup_nhm, poll_nothing}
 };	
 
diff --git a/init.c b/init.c
index b589f28..976c146 100644
--- a/init.c
+++ b/init.c
@@ -3,7 +3,7 @@
  * Released under version 2 of the Gnu Public License.
  * By Chris Brady, cbrady@sgi.com
  * ----------------------------------------------------
- * MemTest86+ V2.10 Specific code (GPL V2.0)
+ * MemTest86+ V2.11 Specific code (GPL V2.0)
  * By Samuel DEMEULEMEESTER, sdemeule@memtest.org
  * http://www.canardpc.com - http://www.memtest.org
  */
@@ -63,7 +63,7 @@ static void display_init(void)
 	for(i=0, pp=(char *)(SCREEN_ADR+1); i<TITLE_WIDTH; i++, pp+=2) {
 		*pp = 0x20;
 	}
-	cprint(0, 0, "      Memtest86  v2.10      ");
+	cprint(0, 0, "      Memtest86  v2.11      ");
 
 	for(i=0, pp=(char *)(SCREEN_ADR+1); i<2; i++, pp+=30) {
 		*pp = 0xA4;
@@ -810,7 +810,7 @@ void cpu_type(void)
 					break;
 				case 10:
 					if (((cpu_id.ext >> 16) & 0xF) != 0) {
-						tsc_invariable = 1;
+						  tsc_invariable = 1;
 							cprint(LINE_CPU, 0, "Intel Core i7");
 							off = 13;
 						} else {
@@ -832,8 +832,14 @@ void cpu_type(void)
 					off = 16;
 					break;
 				case 14:
-					cprint(LINE_CPU, 0, "Intel Core");
-					off = 10;
+					if (((cpu_id.ext >> 16) & 0xF) != 0) {
+						tsc_invariable = 1;
+						cprint(LINE_CPU, 0, "Intel Core i5");
+						off = 13;
+					} else {
+						cprint(LINE_CPU, 0, "Intel Core");
+						off = 10;
+					}
 					break;				
 				case 15:
 					if (l2_cache == 1024) {
@@ -1130,7 +1136,7 @@ static void cacheable(void)
 		}
 		/* Map the range and perform the test */
 		map_page(paddr);
-		speed = memspeed((ulong)mapping(paddr), 32*4096, 1, MS_COPY);
+		speed = memspeed((ulong)mapping(paddr), 32*4096, 1, MS_READ);
 		if (pspeed) {
 			if (speed < pspeed) {
 				cached -= 32;
diff --git a/makeiso.sh b/makeiso.sh
index 70c0b84..7180879 100755
--- a/makeiso.sh
+++ b/makeiso.sh
@@ -37,9 +37,9 @@ cd cd
 echo -e "There is nothing to do here\r\r\nMemtest86+ is located on the bootsector of this CD\r\r\n" > README.TXT
 echo -e "Just boot from this CD and Memtest86+ will launch" >> README.TXT
 
-mkisofs -A "MKISOFS 1.1.2" -p "Memtest86+ 2.10" -publisher "Samuel D. <sdemeule@memtest.org>" -b boot/memtest.img -c boot/boot.catalog -V "MT201" -o memtest.iso .
-mv memtest.iso ../mt210.iso
+mkisofs -A "MKISOFS 1.1.2" -p "Memtest86+ 2.11" -publisher "Samuel D. <sdemeule@memtest.org>" -b boot/memtest.img -c boot/boot.catalog -V "MT201" -o memtest.iso .
+mv memtest.iso ../mt211.iso
 cd ..
 rm -rf cd
 
-echo "Done! Memtest86+ ISO is mt210.iso"
+echo "Done! Memtest86+ ISO is mt211.iso"
diff --git a/mt86+_loader b/mt86+_loader
index 9389305..ee3d2ec 100644
--- a/mt86+_loader
+++ b/mt86+_loader
diff --git a/mt86+_loader.asm b/mt86+_loader.asm
index b47b84d..29b0322 100644
--- a/mt86+_loader.asm
+++ b/mt86+_loader.asm
@@ -12,8 +12,8 @@
 ; The good thing is that you get a single file which can be
 ; compressed, for example with http://upx.sf.net/ (UPX).
 
-%define fullsize (116284 + buffer - exeh)
-	; 116284 is the size of memtest86+ V2.10, adjust as needed!
+%define fullsize (116508 + buffer - exeh)
+	; 116508 is the size of memtest86+ V2.11, adjust as needed!
 
 %define stacksize 2048
 %define stackpara ((stacksize + 15) / 16)
diff --git a/precomp.bin b/precomp.bin
index 3f6cfec..d7f7f2f 100644
--- a/precomp.bin
+++ b/precomp.bin
diff --git a/spd.c b/spd.c
index bac4e12..484bc26 100644
--- a/spd.c
+++ b/spd.c
@@ -114,16 +114,18 @@ struct pci_smbus_controller {
 };

 

 static struct pci_smbus_controller smbcontrollers[] = {

-{0x8086, 0x3A30, "Intel ICH10", ich5_get_smb, ich5_read_spd},

-{0x8086, 0x2930, "Intel ICH9", ich5_get_smb, ich5_read_spd},

-{0x8086, 0x283E, "Intel ICH8", ich5_get_smb, ich5_read_spd},

-{0x8086, 0x27DA, "Intel ICH7", ich5_get_smb, ich5_read_spd},

-{0x8086, 0x266A, "Intel ICH6", ich5_get_smb, ich5_read_spd},

-{0x8086, 0x24D3, "Intel ICH5", ich5_get_smb, ich5_read_spd},

-{0x8086, 0x24C3, "Intel ICH4", ich5_get_smb, ich5_read_spd},

+{0x8086, 0x3B30, "Intel P55", 		ich5_get_smb, ich5_read_spd},

+{0x8086, 0x3A60, "Intel ICH10B", 	ich5_get_smb, ich5_read_spd},

+{0x8086, 0x3A30, "Intel ICH10R", 	ich5_get_smb, ich5_read_spd},

+{0x8086, 0x2930, "Intel ICH9", 		ich5_get_smb, ich5_read_spd},

+{0x8086, 0x283E, "Intel ICH8", 		ich5_get_smb, ich5_read_spd},

+{0x8086, 0x27DA, "Intel ICH7", 		ich5_get_smb, ich5_read_spd},

+{0x8086, 0x266A, "Intel ICH6", 		ich5_get_smb, ich5_read_spd},

+{0x8086, 0x24D3, "Intel ICH5", 		ich5_get_smb, ich5_read_spd},

+{0x8086, 0x24C3, "Intel ICH4", 		ich5_get_smb, ich5_read_spd},

 {0x8086, 0x25A4, "Intel 6300ESB", ich5_get_smb, ich5_read_spd},

-{0x8086, 0x269B, "Intel ESB2", ich5_get_smb, ich5_read_spd},

-{0x8086, 0x8119, "Intel US15W", us15w_get_smb, us15w_read_spd},

+{0x8086, 0x269B, "Intel ESB2", 		ich5_get_smb, ich5_read_spd},

+{0x8086, 0x8119, "Intel US15W", 	us15w_get_smb, us15w_read_spd},

 {0x8086, 0x5032, "Intel EP80579", ich5_get_smb, ich5_read_spd},

 {0, 0, "", NULL, NULL}

 };