diff options
Diffstat (limited to 'controller.c')
| -rw-r--r-- | controller.c | 2531 |
1 files changed, 1486 insertions, 1045 deletions
diff --git a/controller.c b/controller.c index 9009996..f4f7371 100644 --- a/controller.c +++ b/controller.c @@ -1,21 +1,20 @@ -/* controller.c - MemTest-86 Version 3.0 - * - * Released under version 2 of the Gnu Public License. - * By Chris Brady, cbrady@sgi.com - * ---------------------------------------------------- - * MemTest86+ V4.20 Specific code (GPL V2.0) +/* + * MemTest86+ V5 Specific code (GPL V2.0) * By Samuel DEMEULEMEESTER, sdemeule@memtest.org * http://www.canardpc.com - http://www.memtest.org */ -#include "defs.h" +//#include "defs.h" #include "config.h" -#include "test.h" +//#include "test.h" #include "pci.h" #include "controller.h" #include "spd.h" #include "test.h" - +#include "stdint.h" +#include "cpuid.h" +#include "msr.h" +#include "dmi.h" int col, col2; int nhm_bus = 0x3F; @@ -23,18 +22,17 @@ int nhm_bus = 0x3F; extern ulong extclock; extern unsigned long imc_type; extern struct cpu_ident cpu_id; -extern int fail_safe; - +/* #define rdmsr(msr,val1,val2) \ __asm__ __volatile__("rdmsr" \ : "=a" (val1), "=d" (val2) \ - : "c" (msr)) + : "c" (msr) : "edi") #define wrmsr(msr,val1,val2) \ __asm__ __volatile__("wrmsr" \ - : /* no outputs */ \ - : "c" (msr), "a" (val1), "d" (val2)) - + : \ + : "c" (msr), "a" (val1), "d" (val2) : "edi") +*/ /* controller ECC capabilities and mode */ #define __ECC_UNEXPECTED 1 /* Unknown ECC capability present */ #define __ECC_DETECT 2 /* Can detect ECC errors */ @@ -74,115 +72,187 @@ static struct ecc_info { .mode = ECC_UNKNOWN, }; -struct pci_memory_controller { - unsigned vendor; - unsigned device; - char *name; - int tested; - void (*poll_fsb)(void); - void (*poll_timings)(void); - void (*setup_ecc)(void); - void (*poll_errors)(void); -}; +void coretemp(void) +{ + unsigned int msrl, msrh; + unsigned int tjunc, tabs, tnow; + unsigned long rtcr; + double amd_raw_temp; + + // Only enable coretemp if IMC is known + if(imc_type == 0) { return; } + + tnow = 0; + + // Intel CPU + if(cpu_id.vend_id.char_array[0] == 'G' && cpu_id.max_cpuid >= 6) + { + if(cpu_id.dts_pmp & 1){ + rdmsr(MSR_IA32_THERM_STATUS, msrl, msrh); + tabs = ((msrl >> 16) & 0x7F); + rdmsr(MSR_IA32_TEMPERATURE_TARGET, msrl, msrh); + tjunc = ((msrl >> 16) & 0x7F); + if(tjunc < 50 || tjunc > 125) { tjunc = 90; } // assume Tjunc = 90°C if boggus value received. + tnow = tjunc - tabs; + dprint(LINE_CPU+1, 30, v->check_temp, 3, 0); + v->check_temp = tnow; + } + return; + } + + // AMD CPU + if(cpu_id.vend_id.char_array[0] == 'A' && cpu_id.vers.bits.extendedFamily > 0) + { + pci_conf_read(0, 24, 3, 0xA4, 4, &rtcr); + amd_raw_temp = ((rtcr >> 21) & 0x7FF); + v->check_temp = (int)(amd_raw_temp / 8); + dprint(LINE_CPU+1, 30, v->check_temp, 3, 0); + } + + +} + +void print_cpu_line(float dram_freq, float fsb_freq, int ram_type) +{ + int cur_col = COL_SPEC; + + cprint(LINE_CPU, cur_col, "RAM: "); + cur_col += 5; + dprint(LINE_CPU, cur_col, dram_freq, 4, 1); + cur_col += 4; + cprint(LINE_CPU, cur_col, "MHz ("); + cur_col += 5; + + switch(ram_type) + { + default: + case 1: + cprint(LINE_CPU, cur_col, "DDR-"); + cur_col += 4; + break; + case 2: + cprint(LINE_CPU, cur_col, "DDR2-"); + cur_col += 5; + break; + case 3: + cprint(LINE_CPU, cur_col, "DDR3-"); + cur_col += 5; + break; + } + + if(dram_freq < 500) + { + dprint(LINE_CPU, cur_col, dram_freq*2, 3, 0); + cur_col += 3; + } else { + dprint(LINE_CPU, cur_col, dram_freq*2, 4, 0); + cur_col += 4; + } + cprint(LINE_CPU, cur_col, ")"); + cur_col++; + + if(fsb_freq > 10) + { + cprint(LINE_CPU, cur_col, " - BCLK: "); + cur_col += 9; + + dprint(LINE_CPU, cur_col, fsb_freq, 3, 0); + } + +} -void print_timings_info(float cas, int rcd, int rp, int ras) { +void print_ram_line(float cas, int rcd, int rp, int ras, int chan) +{ + int cur_col = COL_SPEC; - /* Now, we could print some additionnals timings infos) */ - cprint(LINE_CPU+6, col2 +1, "/ CAS : "); - col2 += 9; + cprint(LINE_RAM, cur_col, "Timings: CAS "); + cur_col += 13; // CAS Latency (tCAS) if (cas == 1.5) { - cprint(LINE_CPU+6, col2, "1.5"); col2 += 3; + cprint(LINE_RAM, cur_col, "1.5"); cur_col += 3; } else if (cas == 2.5) { - cprint(LINE_CPU+6, col2, "2.5"); col2 += 3; + cprint(LINE_RAM, cur_col, "2.5"); cur_col += 3; } else if (cas < 10) { - dprint(LINE_CPU+6, col2, cas, 1, 0); col2 += 1; + dprint(LINE_RAM, cur_col, cas, 1, 0); cur_col += 1; } else { - dprint(LINE_CPU+6, col2, cas, 2, 0); col2 += 2; + dprint(LINE_RAM, cur_col, cas, 2, 0); cur_col += 2; } - cprint(LINE_CPU+6, col2, "-"); col2 += 1; + cprint(LINE_RAM, cur_col, "-"); cur_col += 1; // RAS-To-CAS (tRCD) if (rcd < 10) { - dprint(LINE_CPU+6, col2, rcd, 1, 0); - col2 += 1; + dprint(LINE_RAM, cur_col, rcd, 1, 0); + cur_col += 1; } else { - dprint(LINE_CPU+6, col2, rcd, 2, 0); - col2 += 2; + dprint(LINE_RAM, cur_col, rcd, 2, 0); + cur_col += 2; } - cprint(LINE_CPU+6, col2, "-"); col2 += 1; + cprint(LINE_RAM, cur_col, "-"); cur_col += 1; // RAS Precharge (tRP) if (rp < 10) { - dprint(LINE_CPU+6, col2, rp, 1, 0); - col2 += 1; + dprint(LINE_RAM, cur_col, rp, 1, 0); + cur_col += 1; } else { - dprint(LINE_CPU+6, col2, rp, 2, 0); - col2 += 2; + dprint(LINE_RAM, cur_col, rp, 2, 0); + cur_col += 2; } - cprint(LINE_CPU+6, col2, "-"); col2 += 1; + cprint(LINE_RAM, cur_col, "-"); cur_col += 1; // RAS Active to precharge (tRAS) if (ras < 10) { - dprint(LINE_CPU+6, col2, ras, 1, 0); - col2 += 2; + dprint(LINE_RAM, cur_col, ras, 1, 0); + cur_col += 1; } else { - dprint(LINE_CPU+6, col2, ras, 2, 0); - col2 += 3; + dprint(LINE_RAM, cur_col, ras, 2, 0); + cur_col += 2; } - -} - -void print_fsb_info(float val, const char *text_fsb, const char *text_ddr) { - - int i; - - cprint(LINE_CPU+6, col2, "Settings: "); - col2 += 10; - cprint(LINE_CPU+6, col2, text_fsb); - col2 += 6; - dprint(LINE_CPU+6, col2, val ,3 ,0); - col2 += 3; - cprint(LINE_CPU+6, col2 +1, "MHz ("); - col2 += 6; - - cprint(LINE_CPU+6, col2, text_ddr); - for(i = 0; text_ddr[i] != '\0'; i++) { col2++; } - - if(val < 500) { - dprint(LINE_CPU+6, col2, val*2 ,3 ,0); - col2 += 3; - } else { - dprint(LINE_CPU+6, col2, val*2 ,4 ,0); - col2 += 4; + + + switch(chan) + { + case 0: + break; + case 1: + cprint(LINE_RAM, cur_col, " @ 64-bit Mode"); + break; + case 2: + cprint(LINE_RAM, cur_col, " @ 128-bit Mode"); + break; + case 3: + cprint(LINE_RAM, cur_col, " @ 192-bit Mode"); + break; + case 4: + cprint(LINE_RAM, cur_col, " @ 256-bit Mode"); + break; } - cprint(LINE_CPU+6, col2, ")"); - col2 += 1; } - - static void poll_fsb_nothing(void) { -/* Code to run for no specific fsb detection */ + + char *name; + + /* Print the controller name */ + name = controllers[ctrl.index].name; + cprint(LINE_CPU, COL_SPEC, "Chipset: "); + cprint(LINE_CPU, COL_SPEC+9, name); return; } static void poll_timings_nothing(void) { -/* Code to run for no specific timings detection */ + char *ram_type; + + /* Print the controller name */ + ram_type = controllers[ctrl.index].ram_type; + cprint(LINE_RAM, COL_SPEC, "RAM Type: "); + cprint(LINE_RAM, COL_SPEC+10, ram_type); return; } -static void poll_fsb_failsafe(void) -{ -/* Code to run for no specific fsb detection */ - cprint(LINE_CPU+5, 0, "Chipset/IMC : ***FAIL SAFE***FAIL SAFE***FAIL SAFE***FAIL SAFE***FAIL SAFE***"); - cprint(LINE_CPU+6, 0, "*** Memtest86+ is running in fail safe mode. Same reliability, less details ***"); - return; -} static void setup_nothing(void) { ctrl.cap = ECC_NONE; @@ -199,18 +269,14 @@ static void poll_nothing(void) static void setup_wmr(void) { - - // Activate MMR I/O ulong dev0; - ctrl.cap = ECC_CORRECT; - + + // Activate MMR I/O pci_conf_read( 0, 0, 0, 0x48, 4, &dev0); if (!(dev0 & 0x1)) { pci_conf_write( 0, 0, 0, 0x48, 1, dev0 | 1); } - ctrl.mode = ECC_NONE; - } @@ -261,7 +327,6 @@ static void setup_nhm32(void) ctrl.mode = ECC_NONE; /* First, locate the PCI bus where the MCH is located */ - for(i = 0; i < sizeof(possible_nhm_bus); i++) { pci_conf_read( possible_nhm_bus[i], 3, 4, 0x00, 2, &vid); pci_conf_read( possible_nhm_bus[i], 3, 4, 0x02, 2, &did); @@ -270,7 +335,7 @@ static void setup_nhm32(void) if(vid == 0x8086 && did >= 0x2C00) { nhm_bus = possible_nhm_bus[i]; } -} + } /* Now, we have the last IMC bus number in nhm_bus */ /* Check for ECC & Scrub */ @@ -287,7 +352,6 @@ static void setup_nhm32(void) static void setup_amd64(void) { - static const int ddim[] = { ECC_NONE, ECC_CORRECT, ECC_RESERVED, ECC_CHIPKILL }; unsigned long nbxcfg; unsigned int mcgsrl; @@ -301,8 +365,7 @@ static void setup_amd64(void) /* Check First if ECC DRAM Modules are used */ pci_conf_read(0, 24, 2, 0x90, 4, &dramcl); - - if (((cpu_id.ext >> 16) & 0xF) >= 4) { + if (cpu_id.vers.bits.extendedModel >= 4) { /* NEW K8 0Fh Family 90 nm */ if ((dramcl >> 19)&1){ @@ -350,24 +413,24 @@ static void setup_k10(void) unsigned long dramcl; ulong msr_low, msr_high; - /* All AMD64 support Chipkill */ + // All AMD64 support Chipkill */ ctrl.cap = ECC_CHIPKILL; - /* Check First if ECC DRAM Modules are used */ + // Check First if ECC DRAM Modules are used */ pci_conf_read(0, 24, 2, 0x90, 4, &dramcl); if ((dramcl >> 19)&1){ - /* Fill in the correct memory capabilites */ + // Fill in the correct memory capabilites */ pci_conf_read(0, 24, 3, 0x44, 4, &nbxcfg); ctrl.mode = ddim[(nbxcfg >> 22)&3]; } else { ctrl.mode = ECC_NONE; } - /* Enable NB ECC Logging by MSR Write */ + // Enable NB ECC Logging by MSR Write */ rdmsr(0x017B, mcgsrl, mcgsth); wrmsr(0x017B, 0x10, mcgsth); - /* Clear any previous error */ + // Clear any previous error */ pci_conf_read(0, 24, 3, 0x4C, 4, &mcanb); pci_conf_write(0, 24, 3, 0x4C, 4, mcanb & 0x7FFFFFFF ); @@ -378,6 +441,19 @@ static void setup_k10(void) } +static void setup_apu(void) +{ + + ulong msr_low, msr_high; + + /* Enable ECS */ + rdmsr(0xC001001F, msr_low, msr_high); + wrmsr(0xC001001F, msr_low, (msr_high | 0x4000)); + rdmsr(0xC001001F, msr_low, msr_high); + +} + +/* static void poll_amd64(void) { @@ -389,42 +465,43 @@ static void poll_amd64(void) pci_conf_read(0, 24, 3, 0x4C, 4, &mcanb); if (((mcanb >> 31)&1) && ((mcanb >> 14)&1)) { - /* Find out about the first correctable error */ - /* Syndrome code -> bits use a complex matrix. Will add this later */ - /* Read the error location */ + // Find out about the first correctable error + // Syndrome code -> bits use a complex matrix. Will add this later + // Read the error location pci_conf_read(0, 24, 3, 0x50, 4, &mcanb_add); - /* Read the syndrome */ + // Read the syndrome celog_syndrome = (mcanb >> 15)&0xFF; - /* Parse the error location */ + // Parse the error location page = (mcanb_add >> 12); offset = (mcanb_add >> 3) & 0xFFF; - /* Report the error */ + // Report the error print_ecc_err(page, offset, 1, celog_syndrome, 0); - /* Clear the error registers */ + // Clear the error registers pci_conf_write(0, 24, 3, 0x4C, 4, mcanb & 0x7FFFFFFF ); } if (((mcanb >> 31)&1) && ((mcanb >> 13)&1)) { - /* Found out about the first uncorrectable error */ - /* Read the error location */ + // Found out about the first uncorrectable error + // Read the error location pci_conf_read(0, 24, 3, 0x50, 4, &mcanb_add); - /* Parse the error location */ + // Parse the error location page = (mcanb_add >> 12); offset = (mcanb_add >> 3) & 0xFFF; - /* Report the error */ + // Report the error print_ecc_err(page, offset, 0, 0, 0); - /* Clear the error registers */ + // Clear the error registers pci_conf_write(0, 24, 3, 0x4C, 4, mcanb & 0x7FFFFFF ); } } +*/ static void setup_amd751(void) { @@ -436,6 +513,7 @@ static void setup_amd751(void) ctrl.mode = (dram_status & (1 << 2))?ECC_CORRECT: ECC_NONE; } +/* static void poll_amd751(void) { unsigned long ecc_status; @@ -445,34 +523,34 @@ static void poll_amd751(void) int bits; int i; - /* Read the error status */ + // Read the error status pci_conf_read(ctrl.bus, ctrl.dev, ctrl.fn, 0x58, 2, &ecc_status); if (ecc_status & (3 << 8)) { for(i = 0; i < 6; i++) { if (!(ecc_status & (1 << i))) { continue; } - /* Find the bank the error occured on */ + // Find the bank the error occured on bank_addr = 0x40 + (i << 1); - /* Now get the information on the erroring bank */ + // Now get the information on the erroring bank pci_conf_read(ctrl.bus, ctrl.dev, ctrl.fn, bank_addr, 2, &bank_info); - /* Parse the error location and error type */ + // Parse the error location and error type page = (bank_info & 0xFF80) << 4; bits = (((ecc_status >> 8) &3) == 2)?1:2; - /* Report the error */ + // Report the error print_ecc_err(page, 0, bits==1?1:0, 0, 0); } - /* Clear the error status */ + // Clear the error status pci_conf_write(ctrl.bus, ctrl.dev, ctrl.fn, 0x58, 2, 0); } } -/* Still waiting for the CORRECT intel datasheet +// Still waiting for the CORRECT intel datasheet static void setup_i85x(void) { unsigned long drc; @@ -495,6 +573,7 @@ static void setup_amd76x(void) ctrl.mode = ddim[(ecc_mode_status >> 10)&3]; } +/* static void poll_amd76x(void) { unsigned long ecc_mode_status; @@ -502,43 +581,44 @@ static void poll_amd76x(void) unsigned long bank_info; unsigned long page; - /* Read the error status */ + // Read the error status pci_conf_read(ctrl.bus, ctrl.dev, ctrl.fn, 0x48, 4, &ecc_mode_status); - /* Multibit error */ + // Multibit error if (ecc_mode_status & (1 << 9)) { - /* Find the bank the error occured on */ + // Find the bank the error occured on bank_addr = 0xC0 + (((ecc_mode_status >> 4) & 0xf) << 2); - /* Now get the information on the erroring bank */ + // Now get the information on the erroring bank pci_conf_read(ctrl.bus, ctrl.dev, ctrl.fn, bank_addr, 4, &bank_info); - /* Parse the error location and error type */ + // Parse the error location and error type page = (bank_info & 0xFF800000) >> 12; - /* Report the error */ + // Report the error print_ecc_err(page, 0, 1, 0, 0); } - /* Singlebit error */ + // Singlebit error if (ecc_mode_status & (1 << 8)) { - /* Find the bank the error occured on */ + // Find the bank the error occured on bank_addr = 0xC0 + (((ecc_mode_status >> 0) & 0xf) << 2); - /* Now get the information on the erroring bank */ + // Now get the information on the erroring bank pci_conf_read(ctrl.bus, ctrl.dev, ctrl.fn, bank_addr, 4, &bank_info); - /* Parse the error location and error type */ + // Parse the error location and error type page = (bank_info & 0xFF800000) >> 12; - /* Report the error */ + // Report the error print_ecc_err(page, 0, 0, 0, 0); } - /* Clear the error status */ + // Clear the error status if (ecc_mode_status & (3 << 8)) { pci_conf_write(ctrl.bus, ctrl.dev, ctrl.fn, 0x48, 4, ecc_mode_status); } } +*/ static void setup_cnb20(void) { @@ -658,8 +738,10 @@ static void setup_iE7520(void) /* Clear any prexisting error reports */ pci_conf_write(ctrl.bus, ctrl.dev, ctrl.fn +1, 0x80, 2, 0x4747); pci_conf_write(ctrl.bus, ctrl.dev, ctrl.fn +1, 0x82, 2, 0x4747); + } +/* static void poll_iE7xxx(void) { unsigned long ferr; @@ -669,50 +751,51 @@ static void poll_iE7xxx(void) pci_conf_read(ctrl.bus, ctrl.dev, ctrl.fn +1, 0x82, 1, &nerr); if (ferr & 1) { - /* Find out about the first correctable error */ + // Find out about the first correctable error unsigned long celog_add; unsigned long celog_syndrome; unsigned long page; - /* Read the error location */ + // Read the error location pci_conf_read(ctrl.bus, ctrl.dev, ctrl.fn +1, 0xA0, 4, &celog_add); - /* Read the syndrome */ + // Read the syndrome pci_conf_read(ctrl.bus, ctrl.dev, ctrl.fn +1, 0xD0, 2, &celog_syndrome); - /* Parse the error location */ + // Parse the error location page = (celog_add & 0x0FFFFFC0) >> 6; - /* Report the error */ + // Report the error print_ecc_err(page, 0, 1, celog_syndrome, 0); - /* Clear Bit */ + // Clear Bit pci_conf_write(ctrl.bus, ctrl.dev, ctrl.fn +1, 0x80, 1, ferr & 3); } if (ferr & 2) { - /* Found out about the first uncorrectable error */ + // Found out about the first uncorrectable error unsigned long uccelog_add; unsigned long page; - /* Read the error location */ + // Read the error location pci_conf_read(ctrl.bus, ctrl.dev, ctrl.fn +1, 0xB0, 4, &uccelog_add); - /* Parse the error location */ + // Parse the error location page = (uccelog_add & 0x0FFFFFC0) >> 6; - /* Report the error */ + // Report the error print_ecc_err(page, 0, 0, 0, 0); - /* Clear Bit */ + // Clear Bit pci_conf_write(ctrl.bus, ctrl.dev, ctrl.fn +1, 0x80, 1, ferr & 3); } - /* Check if DRAM_NERR contains data */ + // Check if DRAM_NERR contains data if (nerr & 3) { pci_conf_write(ctrl.bus, ctrl.dev, ctrl.fn +1, 0x82, 1, nerr & 3); } } +*/ static void setup_i440gx(void) { @@ -725,19 +808,20 @@ static void setup_i440gx(void) ctrl.mode = ddim[(nbxcfg >> 7)&3]; } +/* static void poll_i440gx(void) { unsigned long errsts; unsigned long page; int bits; - /* Read the error status */ + // Read the error status pci_conf_read(ctrl.bus, ctrl.dev, ctrl.fn, 0x91, 2, &errsts); if (errsts & 0x11) { unsigned long eap; - /* Read the error location */ + // Read the error location pci_conf_read(ctrl.bus, ctrl.dev, ctrl.fn, 0x80, 4, &eap); - /* Parse the error location and error type */ + // Parse the error location and error type page = (eap & 0xFFFFF000) >> 12; bits = 0; if (eap &3) { @@ -745,16 +829,19 @@ static void poll_i440gx(void) } if (bits) { - /* Report the error */ + // Report the error print_ecc_err(page, 0, bits==1?1:0, 0, 0); } - /* Clear the error status */ + // Clear the error status pci_conf_write(ctrl.bus, ctrl.dev, ctrl.fn, 0x91, 2, 0x11); pci_conf_write(ctrl.bus, ctrl.dev, ctrl.fn, 0x80, 4, 3); } } +*/ + + static void setup_i840(void) { static const int ddim[] = { ECC_NONE, ECC_RESERVED, ECC_CORRECT, ECC_CORRECT }; @@ -766,6 +853,7 @@ static void setup_i840(void) ctrl.mode = ddim[(mchcfg >> 7)&3]; } +/* static void poll_i840(void) { unsigned long errsts; @@ -773,29 +861,32 @@ static void poll_i840(void) unsigned long syndrome; int channel; int bits; - /* Read the error status */ + // Read the error status pci_conf_read(ctrl.bus, ctrl.dev, ctrl.fn, 0xC8, 2, &errsts); if (errsts & 3) { unsigned long eap; unsigned long derrctl_sts; - /* Read the error location */ + // Read the error location pci_conf_read(ctrl.bus, ctrl.dev, ctrl.fn, 0xE4, 4, &eap); pci_conf_read(ctrl.bus, ctrl.dev, ctrl.fn, 0xE2, 2, &derrctl_sts); - /* Parse the error location and error type */ + // Parse the error location and error type page = (eap & 0xFFFFF800) >> 11; channel = eap & 1; syndrome = derrctl_sts & 0xFF; bits = ((errsts & 3) == 1)?1:2; - /* Report the error */ + // Report the error print_ecc_err(page, 0, bits==1?1:0, syndrome, channel); - /* Clear the error status */ + // Clear the error status pci_conf_write(ctrl.bus, ctrl.dev, ctrl.fn, 0xE2, 2, 3 << 10); pci_conf_write(ctrl.bus, ctrl.dev, ctrl.fn, 0xC8, 2, 3); } } +*/ + + static void setup_i875(void) { @@ -883,8 +974,27 @@ static void setup_p35(void) ctrl.mode = ECC_NONE; + /* + ulong toto; + pci_conf_write(0, 31, 3, 0x40, 1, 0x1); + pci_conf_read(0, 31, 3, 0x0, 4, &toto); + hprint(11,0,toto); + pci_conf_read(0, 31, 3, 0x10, 4, &toto); + hprint(11,10,toto) ; + pci_conf_read(0, 31, 3, 0x20, 4, &toto); + hprint(11,20,toto) ; + pci_conf_read(0, 28, 0, 0x0, 4, &toto); + hprint(11,30,toto); + pci_conf_read(0, 31, 0, 0x0, 4, &toto); + hprint(11,40,toto) ; + pci_conf_read(0, 31, 1, 0x0, 4, &toto); + hprint(11,50,toto) ; + pci_conf_read(0, 31, 2, 0x0, 4, &toto); + hprint(11,60,toto) ; + */ } +/* static void poll_i875(void) { unsigned long errsts; @@ -893,117 +1003,125 @@ static void poll_i875(void) unsigned long syndrome; int channel; int bits; - /* Read the error status */ + // Read the error status pci_conf_read(ctrl.bus, ctrl.dev, ctrl.fn, 0xC8, 2, &errsts); if (errsts & 0x81) { unsigned long eap; unsigned long derrsyn; - /* Read the error location, syndrome and channel */ + // Read the error location, syndrome and channel pci_conf_read(ctrl.bus, ctrl.dev, ctrl.fn, 0x58, 4, &eap); pci_conf_read(ctrl.bus, ctrl.dev, ctrl.fn, 0x5C, 1, &derrsyn); pci_conf_read(ctrl.bus, ctrl.dev, ctrl.fn, 0x5D, 1, &des); - /* Parse the error location and error type */ + // Parse the error location and error type page = (eap & 0xFFFFF000) >> 12; syndrome = derrsyn; channel = des & 1; bits = (errsts & 0x80)?0:1; - /* Report the error */ + // Report the error print_ecc_err(page, 0, bits, syndrome, channel); - /* Clear the error status */ + // Clear the error status pci_conf_write(ctrl.bus, ctrl.dev, ctrl.fn, 0xC8, 2, 0x81); } } +*/ static void setup_i845(void) { static const int ddim[] = { ECC_NONE, ECC_RESERVED, ECC_CORRECT, ECC_RESERVED }; unsigned long drc; - /* Fill in the correct memory capabilites */ + // Fill in the correct memory capabilites pci_conf_read(ctrl.bus, ctrl.dev, ctrl.fn, 0x7C, 4, &drc); ctrl.cap = ECC_CORRECT; ctrl.mode = ddim[(drc >> 20)&3]; } +/* static void poll_i845(void) { unsigned long errsts; unsigned long page, offset; unsigned long syndrome; int bits; - /* Read the error status */ + // Read the error status pci_conf_read(ctrl.bus, ctrl.dev, ctrl.fn, 0xC8, 2, &errsts); if (errsts & 3) { unsigned long eap; unsigned long derrsyn; - /* Read the error location */ + // Read the error location pci_conf_read(ctrl.bus, ctrl.dev, ctrl.fn, 0x8C, 4, &eap); pci_conf_read(ctrl.bus, ctrl.dev, ctrl.fn, 0x86, 1, &derrsyn); - /* Parse the error location and error type */ + // Parse the error location and error type offset = (eap & 0xFE) << 4; page = (eap & 0x3FFFFFFE) >> 8; syndrome = derrsyn; bits = ((errsts & 3) == 1)?1:2; - /* Report the error */ + // Report the error print_ecc_err(page, offset, bits==1?1:0, syndrome, 0); - /* Clear the error status */ + // Clear the error status pci_conf_write(ctrl.bus, ctrl.dev, ctrl.fn, 0xC8, 2, 3); } } +*/ + + static void setup_i820(void) { static const int ddim[] = { ECC_NONE, ECC_RESERVED, ECC_CORRECT, ECC_CORRECT }; unsigned long mchcfg; - /* Fill in the correct memory capabilites */ + // Fill in the correct memory capabilites pci_conf_read(ctrl.bus, ctrl.dev, ctrl.fn, 0xbe, 2, &mchcfg); ctrl.cap = ECC_CORRECT; ctrl.mode = ddim[(mchcfg >> 7)&3]; } +/* static void poll_i820(void) { unsigned long errsts; unsigned long page; unsigned long syndrome; int bits; - /* Read the error status */ + // Read the error status pci_conf_read(ctrl.bus, ctrl.dev, ctrl.fn, 0xC8, 2, &errsts); if (errsts & 3) { unsigned long eap; - /* Read the error location */ + // Read the error location pci_conf_read(ctrl.bus, ctrl.dev, ctrl.fn, 0xc4, 4, &eap); - /* Parse the error location and error type */ + // Parse the error location and error type page = (eap & 0xFFFFF000) >> 4; syndrome = eap & 0xFF; bits = ((errsts & 3) == 1)?1:2; - /* Report the error */ + // Report the error print_ecc_err(page, 0, bits==1?1:0, syndrome, 0); - /* Clear the error status */ + // Clear the error status pci_conf_write(ctrl.bus, ctrl.dev, ctrl.fn, 0xC8, 2, 3); } } +*/ static void setup_i850(void) { static const int ddim[] = { ECC_NONE, ECC_RESERVED, ECC_CORRECT, ECC_RESERVED }; unsigned long mchcfg; - /* Fill in the correct memory capabilites */ + // Fill in the correct memory capabilites pci_conf_read(ctrl.bus, ctrl.dev, ctrl.fn, 0x50, 2, &mchcfg); ctrl.cap = ECC_CORRECT; ctrl.mode = ddim[(mchcfg >> 7)&3]; } +/* static void poll_i850(void) { unsigned long errsts; @@ -1011,28 +1129,29 @@ static void poll_i850(void) unsigned long syndrome; int channel; int bits; - /* Read the error status */ + // Read the error status pci_conf_read(ctrl.bus, ctrl.dev, ctrl.fn, 0xC8, 2, &errsts); if (errsts & 3) { unsigned long eap; unsigned long derrctl_sts; - /* Read the error location */ + // Read the error location pci_conf_read(ctrl.bus, ctrl.dev, ctrl.fn, 0xE4, 4, &eap); pci_conf_read(ctrl.bus, ctrl.dev, ctrl.fn, 0xE2, 2, &derrctl_sts); - /* Parse the error location and error type */ + // Parse the error location and error type page = (eap & 0xFFFFF800) >> 11; channel = eap & 1; syndrome = derrctl_sts & 0xFF; bits = ((errsts & 3) == 1)?1:2; - /* Report the error */ + // Report the error print_ecc_err(page, 0, bits==1?1:0, syndrome, channel); - /* Clear the error status */ + // Clear the error status pci_conf_write(ctrl.bus, ctrl.dev, ctrl.fn, 0xC8, 2, errsts & 3); } } +*/ static void setup_i860(void) { @@ -1040,16 +1159,17 @@ static void setup_i860(void) unsigned long mchcfg; unsigned long errsts; - /* Fill in the correct memory capabilites */ + // Fill in the correct memory capabilites pci_conf_read(ctrl.bus, ctrl.dev, ctrl.fn, 0x50, 2, &mchcfg); ctrl.cap = ECC_CORRECT; ctrl.mode = ddim[(mchcfg >> 7)&3]; - /* Clear any prexisting error reports */ + // Clear any prexisting error reports pci_conf_read(ctrl.bus, ctrl.dev, ctrl.fn, 0xC8, 2, &errsts); pci_conf_write(ctrl.bus, ctrl.dev, ctrl.fn, 0xC8, 2, errsts & 3); } +/* static void poll_i860(void) { unsigned long errsts; @@ -1057,29 +1177,30 @@ static void poll_i860(void) unsigned char syndrome; int channel; int bits; - /* Read the error status */ + // Read the error status pci_conf_read(ctrl.bus, ctrl.dev, ctrl.fn, 0xC8, 2, &errsts); if (errsts & 3) { unsigned long eap; unsigned long derrctl_sts; - /* Read the error location */ + // Read the error location pci_conf_read(ctrl.bus, ctrl.dev, ctrl.fn, 0xE4, 4, &eap); pci_conf_read(ctrl.bus, ctrl.dev, ctrl.fn, 0xE2, 2, &derrctl_sts); - /* Parse the error location and error type */ + // Parse the error location and error type page = (eap & 0xFFFFFE00) >> 9; channel = eap & 1; syndrome = derrctl_sts & 0xFF; bits = ((errsts & 3) == 1)?1:2; - /* Report the error */ + // Report the error print_ecc_err(page, 0, bits==1?1:0, syndrome, channel); - /* Clear the error status */ + // Clear the error status pci_conf_write(ctrl.bus, ctrl.dev, ctrl.fn, 0xC8, 2, errsts & 3); } } + static void poll_iE7221(void) { unsigned long errsts; @@ -1097,11 +1218,11 @@ static void poll_iE7221(void) unsigned long eap, offset; unsigned long derrctl_sts; - /* Read the error location */ + // Read the error location pci_conf_read(ctrl.bus, ctrl.dev, ctrl.fn, 0x58, 4, &eap); pci_conf_read(ctrl.bus, ctrl.dev, ctrl.fn, 0x5C, 1, &derrctl_sts); - /* Parse the error location and error type */ + // Parse the error location and error type channel = eap & 1; eap = eap & 0xFFFFFF80; page = eap >> 12; @@ -1109,10 +1230,10 @@ static void poll_iE7221(void) syndrome = derrctl_sts & 0xFF; bits = errocc & 1; - /* Report the error */ + // Report the error print_ecc_err(page, offset, bits, syndrome, channel); - /* Clear the error status */ + // Clear the error status pci_conf_write(ctrl.bus, ctrl.dev, ctrl.fn, 0xC8, 2, errsts & 3); } @@ -1123,6 +1244,7 @@ static void poll_iE7221(void) } } + static void poll_iE7520(void) { unsigned long ferr; @@ -1132,54 +1254,54 @@ static void poll_iE7520(void) pci_conf_read(ctrl.bus, ctrl.dev, ctrl.fn +1, 0x82, 2, &nerr); if (ferr & 0x0101) { - /* Find out about the first correctable error */ + // Find out about the first correctable error unsigned long celog_add; unsigned long celog_syndrome; unsigned long page; - /* Read the error location */ + // Read the error location pci_conf_read(ctrl.bus, ctrl.dev, ctrl.fn +1, 0xA0, 4,&celog_add); - /* Read the syndrome */ + // Read the syndrome pci_conf_read(ctrl.bus, ctrl.dev, ctrl.fn +1, 0xC4, 2, &celog_syndrome); - /* Parse the error location */ + // Parse the error location page = (celog_add & 0x7FFFFFFC) >> 2; - /* Report the error */ + // Report the error print_ecc_err(page, 0, 1, celog_syndrome, 0); - /* Clear Bit */ + // Clear Bit pci_conf_write(ctrl.bus, ctrl.dev, ctrl.fn +1, 0x80, 2, ferr& 0x0101); } if (ferr & 0x4646) { - /* Found out about the first uncorrectable error */ + // Found out about the first uncorrectable error unsigned long uccelog_add; unsigned long page; - /* Read the error location */ + // Read the error location pci_conf_read(ctrl.bus, ctrl.dev, ctrl.fn +1, 0xA4, 4, &uccelog_add); - /* Parse the error location */ + // Parse the error location page = (uccelog_add & 0x7FFFFFFC) >> 2; - /* Report the error */ + // Report the error print_ecc_err(page, 0, 0, 0, 0); - /* Clear Bit */ + // Clear Bit pci_conf_write(ctrl.bus, ctrl.dev, ctrl.fn +1, 0x80, 2, ferr & 0x4646); } - /* Check if DRAM_NERR contains data */ + // Check if DRAM_NERR contains data if (nerr & 0x4747) { pci_conf_write(ctrl.bus, ctrl.dev, ctrl.fn +1, 0x82, 2, nerr & 0x4747); } } +*/ - -/* ------------------ Here the code for FSB detection ------------------ */ +/* ----------------- Here's the code for FSB detection ----------------- */ /* --------------------------------------------------------------------- */ static float athloncoef[] = {11, 11.5, 12.0, 12.5, 5.0, 5.5, 6.0, 6.5, 7.0, 7.5, 8.0, 8.5, 9.0, 9.5, 10.0, 10.5}; @@ -1188,15 +1310,25 @@ static float p4model1ratios[] = {16, 17, 18, 19, 20, 21, 22, 23, 8, 9, 10, 11, 1 static float getP4PMmultiplier(void) { - unsigned int msr_lo, msr_hi; + //unsigned int msr_lo, msr_hi; + int msr_lo, msr_hi; float coef; - /* Find multiplier (by MSR) */ - if (cpu_id.type == 6) { - if((cpu_id.feature_flag >> 7) & 1) { + + /* Find multiplier (by MSR) */ + if (cpu_id.vers.bits.family == 6) + { + if(cpu_id.fid.bits.eist & 1) + { rdmsr(0x198, msr_lo, msr_hi); - coef = ((msr_lo >> 8) & 0x1F); - if ((msr_lo >> 14) & 0x1) { coef = coef + 0.5f; } + coef = ((msr_lo) >> 8) & 0x1F; + if ((msr_lo >> 14) & 0x1) { coef += 0.5f; } + // Atom Fix + if(coef == 6) + { + coef = ((msr_hi) >> 8) & 0x1F; + if ((msr_hi >> 14) & 0x1) { coef += 0.5f; } + } } else { rdmsr(0x2A, msr_lo, msr_hi); coef = (msr_lo >> 22) & 0x1F; @@ -1204,7 +1336,7 @@ static float getP4PMmultiplier(void) } else { - if (cpu_id.model < 2) + if (cpu_id.vers.bits.model < 2) { rdmsr(0x2A, msr_lo, msr_hi); coef = (msr_lo >> 8) & 0xF; @@ -1216,6 +1348,7 @@ static float getP4PMmultiplier(void) coef = (msr_lo >> 24) & 0x1F; } } + return coef; } @@ -1236,75 +1369,51 @@ static float getNHMmultiplier(void) return coef; } - static float getSNBmultiplier(void) { unsigned int msr_lo, msr_hi; float coef; - rdmsr(0x198, msr_lo, msr_hi); - coef = (msr_lo >> 8) & 0xFF; - if(coef < 4) - { - rdmsr(0xCE, msr_lo, msr_hi); - coef = (msr_lo >> 16) & 0xFF; - } - - + rdmsr(0xCE, msr_lo, msr_hi); + coef = (msr_lo >> 8) & 0xFF; return coef; } - -void getIntelPNS(void) +static void poll_fsb_ct(void) { - int i,j; - long psn_eax, psn_ebx, psn_ecx, psn_edx; - long char_hex; - long ocpuid = 0x80000002; - - for(j = 0; j < 4; j++) - { - - asm __volatile__( - "pushl %%ebx\n\t" \ - "cpuid\n\t" \ - "movl %%ebx, %1\n\t" \ - "popl %%ebx\n\t" \ - : "=a" (psn_eax), "=r" (psn_ebx), "=c" (psn_ecx), "=d" (psn_edx) - : "a" (ocpuid) - : "cc" - ); - + unsigned long mcr, mdr; + double dramratio, dramclock, fsb; + float coef = getP4PMmultiplier(); - for(i = 0; i < 4; i++) - { - char_hex = (psn_eax >> (i*8)) & 0xff; - cprint(LINE_CPU+5, col + i, convert_hex_to_char(char_hex)); + /* Build the MCR Message*/ + mcr = (0x10 << 24); // 10h = Read - 11h = Write + mcr += (0x01 << 16); // DRAM Registers located on port 01h + mcr += (0x01 << 8); // DRP = 00h, DTR0 = 01h, DTR1 = 02h, DTR2 = 03h + mcr &= 0xFFFFFFF0; // bit 03:00 RSVD - char_hex = (psn_ebx >> (i*8)) & 0xff; - cprint(LINE_CPU+5, col + i + 4, convert_hex_to_char(char_hex)); - - if(psn_ecx != 0x20202020) - { - char_hex = (psn_ecx >> (i*8)) & 0xff; - cprint(LINE_CPU+5, col + i + 8, convert_hex_to_char(char_hex)); - - char_hex = (psn_edx >> (i*8)) & 0xff; - cprint(LINE_CPU+5, col + i + 12, convert_hex_to_char(char_hex)); - } - else - { - char_hex = (psn_edx >> (i*8)) & 0xff; - cprint(LINE_CPU+5, col + i + 8, convert_hex_to_char(char_hex)); - } - } - (psn_ecx != 0x20202020)?(col += 16):(col +=12); - if(psn_edx == 0x20202020) { col -= 4; } - ocpuid++; - } + /* Send Message to GMCH */ + pci_conf_write(0, 0, 0, 0xD0, 4, mcr); + + /* Read Answer from Sideband bus */ + pci_conf_read(0, 0, 0, 0xD4, 4, &mdr); - col -= 16; + /* Get RAM ratio */ + switch (mdr & 0x3) { + default: + case 0: dramratio = 3.0f; break; + case 1: dramratio = 4.0f; break; + case 2: dramratio = 5.0f; break; + case 3: dramratio = 6.0f; break; + } + + // Compute FSB & RAM Frequency + fsb = ((extclock / 1000) / coef); + dramclock = fsb * dramratio; + + // Print'em all. Whoa ! + print_cpu_line(dramclock, fsb, 3); + } static void poll_fsb_amd64(void) { @@ -1315,12 +1424,16 @@ static void poll_fsb_amd64(void) { unsigned long dramchr; float clockratio; double dramclock; + unsigned int dummy[3]; + int ram_type; float coef = 10; + cpuid(0x80000007, &dummy[0], &dummy[1], &dummy[2], &dummy[3]); + /* First, got the FID by MSR */ /* First look if Cool 'n Quiet is supported to choose the best msr */ - if (((cpu_id.pwrcap >> 1) & 1) == 1) { + if (((dummy[3] >> 1) & 1) == 1) { rdmsr(0xc0010042, mcgsrl, mcgsth); fid = (mcgsrl & 0x3F); } else { @@ -1335,12 +1448,12 @@ static void poll_fsb_amd64(void) { if (fid & 1) { coef = coef + 0.5; } /* Next, we need the clock ratio */ - - if (((cpu_id.ext >> 16) & 0xF) >= 4) { + if (cpu_id.vers.bits.extendedModel >= 4) { /* K8 0FH */ pci_conf_read(0, 24, 2, 0x94, 4, &dramchr); temp2 = (dramchr & 0x7); clockratio = coef; + ram_type = 2; switch (temp2) { case 0x0: @@ -1361,6 +1474,7 @@ static void poll_fsb_amd64(void) { /* OLD K8 */ pci_conf_read(0, 24, 2, 0x94, 4, &dramchr); temp2 = (dramchr >> 20) & 0x7; + ram_type = 1; clockratio = coef; switch (temp2) { @@ -1386,10 +1500,10 @@ static void poll_fsb_amd64(void) { } /* Compute the final DRAM Clock */ - dramclock = (extclock /1000) / clockratio; + dramclock = (extclock / 1000) / clockratio; /* ...and print */ - print_fsb_info(dramclock, "RAM : ", "DDR"); + print_cpu_line(dramclock, (extclock / 1000 / coef), ram_type); } @@ -1401,30 +1515,9 @@ static void poll_fsb_k10(void) { unsigned long dramchr; unsigned long mainPllId; double dramclock; - unsigned long pns_low; - unsigned long pns_high; - unsigned long msr_psn; - - - /* If ECC not enabled : display CPU name as IMC */ - if(ctrl.mode == ECC_NONE) - { - cprint(LINE_CPU+5, 0, "IMC : "); - for(msr_psn = 0; msr_psn < 5; msr_psn++) - { - rdmsr(0xC0010030+msr_psn, pns_low, pns_high); - cprint(LINE_CPU+5, 6+(msr_psn*8), convert_hex_to_char(pns_low & 0xff)); - cprint(LINE_CPU+5, 7+(msr_psn*8), convert_hex_to_char((pns_low >> 8) & 0xff)); - cprint(LINE_CPU+5, 8+(msr_psn*8), convert_hex_to_char((pns_low >> 16) & 0xff)); - cprint(LINE_CPU+5, 9+(msr_psn*8), convert_hex_to_char((pns_low >> 24) & 0xff)); - cprint(LINE_CPU+5, 10+(msr_psn*8), convert_hex_to_char(pns_high & 0xff)); - cprint(LINE_CPU+5, 11+(msr_psn*8), convert_hex_to_char((pns_high >> 8) & 0xff)); - cprint(LINE_CPU+5, 12+(msr_psn*8), convert_hex_to_char((pns_high >> 16) & 0xff)); - cprint(LINE_CPU+5, 13+(msr_psn*8), convert_hex_to_char((pns_high >> 24) & 0xff)); - } - cprint(LINE_CPU+5, 41, "(ECC : Disabled)"); - } - + ulong offset = 0; + int ram_type = 2; + /* First, we need the clock ratio */ pci_conf_read(0, 24, 2, 0x94, 4, &dramchr); temp2 = (dramchr & 0x7); @@ -1437,16 +1530,14 @@ static void poll_fsb_k10(void) { default: temp2 += 3; } - /* Compute the final DRAM Clock */ - if (((cpu_id.ext >> 20) & 0xFF) == 1) + if (((cpu_id.vers.bits.extendedModel >> 4) & 0xFF) == 1) { dramclock = ((temp2 * 200) / 3.0) + 0.25; - else { + } else { unsigned long target; unsigned long dx; unsigned divisor; - target = temp2 * 400; /* Get the FID by MSR */ @@ -1470,75 +1561,262 @@ static void poll_fsb_k10(void) { if ( (dx / divisor) <= target ) break; + + pci_conf_read(0, 24, 2, 0x94, 4, &dramchr); + + // If Channel A not enabled, switch to channel B + if(((dramchr>>14) & 0x1)) + { + offset = 0x100; + pci_conf_read(0, 24, 2, 0x94+offset, 4, &dramchr); + } + + //DDR2 or DDR3 + if ((dramchr >> 8)&1) { + ram_type = 3; + } else { + ram_type = 2;; + } + dramclock = ((dx / divisor) / 6.0) + 0.25; -/* - * dramclock = ((((dx * extclock) / divisor) / (mainPllId+8)) / 600000.0) + 0.25; - */ } /* ...and print */ - print_fsb_info(dramclock, "RAM : ", "DDR"); + print_cpu_line(dramclock, 0, ram_type); } -static void poll_fsb_k14(void) { +static void poll_fsb_k12(void) { unsigned long temp2; unsigned long dramchr; - double dramclock; - unsigned long pns_low; - unsigned long pns_high; - unsigned long msr_psn; + double dramratio, dramclock, fsb, did; + unsigned int mcgsrl,mcgsth, fid, did_raw; + + // Get current FID & DID + rdmsr(0xc0010071, mcgsrl, mcgsth); + did_raw = mcgsrl & 0xF; + fid = (mcgsrl >> 4) & 0xF; + + switch(did_raw) + { + default: + case 0x0: + did = 1.0f; + break; + case 0x1: + did = 1.5f; + break; + case 0x2: + did = 2.0f; + break; + case 0x3: + did = 3.0f; + break; + case 0x4: + did = 4.0f; + break; + case 0x5: + did = 6.0f; + break; + case 0x6: + did = 8.0f; + break; + case 0x7: + did = 12.0f; + break; + case 0x8: + did = 16.0f; + break; + } + + fsb = ((extclock / 1000.0f) / ((fid + 16.0f) / did)); + + /* Finaly, we need the clock ratio */ + pci_conf_read(0, 24, 2, 0x94, 4, &dramchr); + + if(((dramchr >> 14) & 0x1) == 1) + { + pci_conf_read(0, 24, 2, 0x194, 4, &dramchr); + } + + temp2 = (dramchr & 0x1F); + switch (temp2) { + default: + case 0x06: + dramratio = 4.0f; + break; + case 0x0A: + dramratio = 16.0f / 3.0f; + break; + case 0x0E: + dramratio = 20.0f / 3.0f; + break; + case 0x12: + dramratio = 8.0f; + break; + case 0x16: + dramratio = 28.0f / 3.0f; + break; + } + + dramclock = fsb * dramratio; + + /* print */ + print_cpu_line(dramclock, fsb, 3); - /* If ECC not enabled : display CPU name as IMC */ - if(ctrl.mode == ECC_NONE) - { - cprint(LINE_CPU+5, 0, "IMC : "); - for(msr_psn = 0; msr_psn < 5; msr_psn++) - { - rdmsr(0xC0010030+msr_psn, pns_low, pns_high); - cprint(LINE_CPU+5, 6+(msr_psn*8), convert_hex_to_char(pns_low & 0xff)); - cprint(LINE_CPU+5, 7+(msr_psn*8), convert_hex_to_char((pns_low >> 8) & 0xff)); - cprint(LINE_CPU+5, 8+(msr_psn*8), convert_hex_to_char((pns_low >> 16) & 0xff)); - cprint(LINE_CPU+5, 9+(msr_psn*8), convert_hex_to_char((pns_low >> 24) & 0xff)); - cprint(LINE_CPU+5, 10+(msr_psn*8), convert_hex_to_char(pns_high & 0xff)); - cprint(LINE_CPU+5, 11+(msr_psn*8), convert_hex_to_char((pns_high >> 8) & 0xff)); - cprint(LINE_CPU+5, 12+(msr_psn*8), convert_hex_to_char((pns_high >> 16) & 0xff)); - cprint(LINE_CPU+5, 13+(msr_psn*8), convert_hex_to_char((pns_high >> 24) & 0xff)); - } - cprint(LINE_CPU+5, 41, "(ECC : Disabled)"); - } +} - /* First, we need the clock ratio */ - pci_conf_read(0, 24, 2, 0x94, 4, &dramchr); - temp2 = (dramchr & 0x1F); +static void poll_fsb_k16(void) +{ - switch (temp2) { - default: - case 6: - dramclock = 400; - break; - case 10: - dramclock = 533; - break; - case 14: - dramclock = 667; - break; - } + unsigned long dramchr; + double dramratio, dramclock, fsb; + + // FIXME: Unable to find a real way to detect multiplier. + fsb = 100.0f; + + /* Clock ratio */ + pci_conf_read(0, 24, 2, 0x94, 4, &dramchr); + + switch (dramchr & 0x1F) { + default: + case 0x04: /* 333 */ + dramratio = 10.0f / 3.0f; + break; + case 0x06: /* 400 */ + dramratio = 4.0f; + break; + case 0x0A: /* 533 */ + dramratio = 16.0f / 3.0f; + break; + case 0x0E: /* 667 */ + dramratio = 20.0f / 3.0f; + break; + case 0x12: /* 800 */ + dramratio = 8.0f; + break; + case 0x16: /* 933 */ + dramratio = 28.0f / 3.0f; + break; + case 0x19: /* 1050 */ + dramratio = 21.0f / 2.0f; + break; + case 0x1A: /* 1066 */ + dramratio = 32.0f / 3.0f; + break; + } + + dramclock = fsb * dramratio; + + /* print */ + print_cpu_line(dramclock, fsb, 3); + +} + +static void poll_fsb_k15(void) { + + unsigned long temp2; + unsigned long dramchr; + double dramratio, dramclock, fsb; + unsigned int mcgsrl,mcgsth, fid, did; + + // Get current FID & DID + rdmsr(0xc0010071, mcgsrl, mcgsth); + fid = mcgsrl & 0x3F; + did = (mcgsrl >> 6) & 0x7; + + fsb = ((extclock / 1000.0f) / ((fid + 16.0f) / (2^did)) / 2); + + /* Finaly, we need the clock ratio */ + pci_conf_read(0, 24, 2, 0x94, 4, &dramchr); + + if(((dramchr >> 14) & 0x1) == 1) + { + pci_conf_read(0, 24, 2, 0x194, 4, &dramchr); + } + + temp2 = (dramchr & 0x1F); + + switch (temp2) { + case 0x04: + dramratio = 10.0f / 3.0f; + break; + default: + case 0x06: + dramratio = 4.0f; + break; + case 0x0A: + dramratio = 16.0f / 3.0f; + break; + case 0x0E: + dramratio = 20.0f / 3.0f; + break; + case 0x12: + dramratio = 8.0f; + break; + case 0x16: + dramratio = 28.0f / 3.0f; + break; + case 0x1A: + dramratio = 32.0f / 3.0f; + break; + case 0x1F: + dramratio = 36.0f / 3.0f; + break; + } + + dramclock = fsb * dramratio; + + /* print */ + print_cpu_line(dramclock, fsb, 3); + +} +static void poll_fsb_k14(void) +{ + + unsigned long dramchr; + double dramratio, dramclock, fsb; + // FIXME: Unable to find a real way to detect multiplier. + fsb = 100.0f; + + /* Clock ratio */ + pci_conf_read(0, 24, 2, 0x94, 4, &dramchr); + + switch (dramchr & 0x1F) { + default: + case 0x06: + dramratio = 4.0f; + break; + case 0x0A: + dramratio = 16.0f / 3.0f; + break; + case 0x0E: + dramratio = 20.0f / 3.0f; + break; + case 0x12: + dramratio = 8.0f; + break; + } + + dramclock = fsb * dramratio; + /* print */ - print_fsb_info(dramclock, "RAM : ", "DDR-"); + print_cpu_line(dramclock, fsb, 3); } + static void poll_fsb_i925(void) { double dramclock, dramratio, fsb; unsigned long mchcfg, mchcfg2, dev0, drc, idetect; float coef = getP4PMmultiplier(); long *ptr; + int ddr_type; pci_conf_read( 0, 0, 0, 0x02, 2, &idetect); @@ -1556,8 +1834,10 @@ static void poll_fsb_i925(void) { if ((drc&3) != 2) { // We are in DDR1 Mode if (mchcfg2 == 1) { dramratio = 0.8; } else { dramratio = 1; } + ddr_type = 1; } else { // We are in DDR2 Mode + ddr_type = 2; if ((mchcfg >> 2)&1) { // We are in FSB1066 Mode if (mchcfg2 == 2) { dramratio = 0.75; } else { dramratio = 1; } @@ -1581,16 +1861,8 @@ static void poll_fsb_i925(void) { fsb = ((extclock / 1000) / coef); dramclock = fsb * dramratio; - // Print DRAM Freq - print_fsb_info(dramclock, "RAM : ", "DDR"); - /* Print FSB (only if ECC is not enabled) */ - cprint(LINE_CPU+5, col +1, "- FSB : "); - col += 9; - dprint(LINE_CPU+5, col, fsb, 3,0); - col += 3; - cprint(LINE_CPU+5, col +1, "MHz"); - col += 4; + print_cpu_line(dramclock, fsb, ddr_type); } @@ -1617,21 +1889,72 @@ static void poll_fsb_i945(void) { // Compute RAM Frequency fsb = ((extclock / 1000) / coef); + dramclock = fsb * dramratio; - // Print DRAM Freq - print_fsb_info(dramclock, "RAM : ", "DDR"); + // Print + print_cpu_line(dramclock, fsb, 2); - /* Print FSB (only if ECC is not enabled) */ - cprint(LINE_CPU+5, col +1, "- FSB : "); - col += 9; - dprint(LINE_CPU+5, col, fsb, 3,0); - col += 3; - cprint(LINE_CPU+5, col +1, "MHz"); - col += 4; +} + +static void poll_fsb_i945gme(void) { + + double dramclock, dramratio, fsb; + unsigned long mchcfg, dev0, fsb_mch; + float coef = getP4PMmultiplier(); + long *ptr; + + /* Find dramratio */ + pci_conf_read( 0, 0, 0, 0x44, 4, &dev0); + dev0 &= 0xFFFFC000; + ptr=(long*)(dev0+0xC00); + mchcfg = *ptr & 0xFFFF; + dramratio = 1; + + switch (mchcfg & 7) { + case 0: fsb_mch = 400; break; + default: + case 1: fsb_mch = 533; break; + case 2: fsb_mch = 667; break; + } + + + switch (fsb_mch) { + case 400: + switch ((mchcfg >> 4)&7) { + case 2: dramratio = 1.0f; break; + case 3: dramratio = 4.0f/3.0f; break; + case 4: dramratio = 5.0f/3.0f; break; + } + break; + + default: + case 533: + switch ((mchcfg >> 4)&7) { + case 2: dramratio = 3.0f/4.0f; break; + case 3: dramratio = 1.0f; break; + case 4: dramratio = 5.0f/4.0f; break; + } + break; + + case 667: + switch ((mchcfg >> 4)&7) { + case 2: dramratio = 3.0f/5.0f; break; + case 3: dramratio = 4.0f/5.0f; break; + case 4: dramratio = 1.0f; break; + } + break; + } + + // Compute RAM Frequency + fsb = ((extclock / 1000) / coef); + dramclock = fsb * dramratio * 2; + + print_cpu_line(dramclock, fsb, 2); } + static void poll_fsb_i975(void) { double dramclock, dramratio, fsb; @@ -1681,23 +2004,13 @@ static void poll_fsb_i975(void) { case 4: dramratio = 1.5; break; } break; -} - + } // Compute RAM Frequency fsb = ((extclock / 1000) / coef); dramclock = fsb * dramratio; - // Print DRAM Freq - print_fsb_info(dramclock, "RAM : ", "DDR"); - - /* Print FSB (only if ECC is not enabled) */ - cprint(LINE_CPU+5, col +1, "- FSB : "); - col += 9; - dprint(LINE_CPU+5, col, fsb, 3,0); - col += 3; - cprint(LINE_CPU+5, col +1, "MHz"); - col += 4; + print_cpu_line(dramclock, fsb, 2); } @@ -1740,7 +2053,7 @@ static void poll_fsb_i965(void) { case 0: dramratio = 1.0; break; case 1: dramratio = 5.0f/4.0f; break; case 2: dramratio = 5.0f/3.0f; break; - case 3: dramratio = 2.0; break; + case 3: dramratio = 2.0f; break; case 4: dramratio = 8.0f/3.0f; break; case 5: dramratio = 10.0f/3.0f; break; } @@ -1781,15 +2094,127 @@ static void poll_fsb_i965(void) { dramclock = fsb * dramratio; // Print DRAM Freq - print_fsb_info(dramclock, "RAM : ", "DDR"); + print_cpu_line(dramclock, fsb, 2); - /* Print FSB (only if ECC is not enabled) */ - cprint(LINE_CPU+5, col +1, "- FSB : "); - col += 9; - dprint(LINE_CPU+5, col, fsb, 3,0); - col += 3; - cprint(LINE_CPU+5, col +1, "MHz"); - col += 4; +} + +static void poll_fsb_p35(void) { + + double dramclock, dramratio, fsb; + unsigned long mchcfg, dev0, fsb_mch, Device_ID, Memory_Check, c0ckectrl, offset; + float coef = getP4PMmultiplier(); + long *ptr; + int ram_type; + + pci_conf_read( 0, 0, 0, 0x02, 2, &Device_ID); + Device_ID &= 0xFFFF; + + /* Find dramratio */ + pci_conf_read( 0, 0, 0, 0x48, 4, &dev0); + dev0 &= 0xFFFFC000; + + ptr = (long*)(dev0+0x260); + c0ckectrl = *ptr & 0xFFFFFFFF; + + + // If DIMM 0 not populated, check DIMM 1 + ((c0ckectrl) >> 20 & 0xF)?(offset = 0):(offset = 0x400); + + ptr=(long*)(dev0+0xC00); + mchcfg = *ptr & 0xFFFF; + dramratio = 1; + + switch (mchcfg & 7) { + case 0: fsb_mch = 1066; break; + case 1: fsb_mch = 533; break; + default: case 2: fsb_mch = 800; break; + case 3: fsb_mch = 667; break; + case 4: fsb_mch = 1333; break; + case 6: fsb_mch = 1600; break; + } + + + switch (fsb_mch) { + case 533: + switch ((mchcfg >> 4)&7) { + case 1: dramratio = 2.0; break; + case 2: dramratio = 2.5; break; + case 3: dramratio = 3.0; break; + } + break; + + default: + case 800: + switch ((mchcfg >> 4)&7) { + case 0: dramratio = 1.0; break; + case 1: dramratio = 5.0f/4.0f; break; + case 2: dramratio = 5.0f/3.0f; break; + case 3: dramratio = 2.0; break; + case 4: dramratio = 8.0f/3.0f; break; + case 5: dramratio = 10.0f/3.0f; break; + } + break; + + case 1066: + switch ((mchcfg >> 4)&7) { + case 1: dramratio = 1.0f; break; + case 2: dramratio = 5.0f/4.0f; break; + case 3: dramratio = 3.0f/2.0f; break; + case 4: dramratio = 2.0f; break; + case 5: dramratio = 5.0f/2.0f; break; + } + break; + + case 1333: + switch ((mchcfg >> 4)&7) { + case 2: dramratio = 1.0f; break; + case 3: dramratio = 6.0f/5.0f; break; + case 4: dramratio = 8.0f/5.0f; break; + case 5: dramratio = 2.0f; break; + } + break; + + case 1600: + switch ((mchcfg >> 4)&7) { + case 3: dramratio = 1.0f; break; + case 4: dramratio = 4.0f/3.0f; break; + case 5: dramratio = 3.0f/2.0f; break; + case 6: dramratio = 2.0f; break; + } + break; + + } + + // On P45, check 1A8 + if(Device_ID > 0x2E00 && imc_type != 8) { + ptr = (long*)(dev0+offset+0x1A8); + Memory_Check = *ptr & 0xFFFFFFFF; + Memory_Check >>= 2; + Memory_Check &= 1; + Memory_Check = !Memory_Check; + } else if (imc_type == 8) { + ptr = (long*)(dev0+offset+0x224); + Memory_Check = *ptr & 0xFFFFFFFF; + Memory_Check &= 1; + Memory_Check = !Memory_Check; + } else { + ptr = (long*)(dev0+offset+0x1E8); + Memory_Check = *ptr & 0xFFFFFFFF; + } + + //Determine DDR-II or DDR-III + if (Memory_Check & 1) { + ram_type = 2; + } else { + ram_type = 3; + } + + // Compute RAM Frequency + fsb = ((extclock / 1000) / coef); + dramclock = fsb * dramratio; + + // Print DRAM Freq + print_cpu_line(dramclock, fsb, ram_type); } @@ -1856,15 +2281,7 @@ static void poll_fsb_im965(void) { dramclock = fsb * dramratio; // Print DRAM Freq - print_fsb_info(dramclock, "RAM : ", "DDR"); - - /* Print FSB (only if ECC is not enabled) */ - cprint(LINE_CPU+5, col +1, "- FSB : "); - col += 9; - dprint(LINE_CPU+5, col, fsb, 3,0); - col += 3; - cprint(LINE_CPU+5, col +1, "MHz"); - col += 4; + print_cpu_line(dramclock, fsb, 2); } @@ -1905,15 +2322,7 @@ static void poll_fsb_5400(void) { dramclock = fsb * dramratio; // Print DRAM Freq - print_fsb_info(dramclock, "RAM : ", "DDR"); - - /* Print FSB (only if ECC is not enabled) */ - cprint(LINE_CPU+5, col +1, "- FSB : "); - col += 9; - dprint(LINE_CPU+5, col, fsb, 3,0); - col += 3; - cprint(LINE_CPU+5, col +1, "MHz"); - col += 4; + print_cpu_line(dramclock, fsb, 2); } @@ -1946,16 +2355,8 @@ static void poll_fsb_nf4ie(void) { fsb = ((extclock /1000) / coef); dramclock = fsb * dramratio; - /* Print DRAM Freq */ - print_fsb_info(dramclock, "RAM : ", "DDR"); - - /* Print FSB */ - cprint(LINE_CPU+5, col, "- FSB : "); - col += 9; - dprint(LINE_CPU+5, col, fsb, 3,0); - col += 3; - cprint(LINE_CPU+5, col +1, "MHz"); - col += 4; + // Print DRAM Freq + print_cpu_line(dramclock, fsb, 2); } @@ -1989,38 +2390,45 @@ static void poll_fsb_i875(void) { fsb = ((extclock /1000) / coef); /* Print DRAM Freq */ - print_fsb_info(dramclock, "RAM : ", "DDR"); - - /* Print FSB (only if ECC is not enabled) */ - if ( ctrl.mode == ECC_NONE ) { - cprint(LINE_CPU+5, col +1, "- FSB : "); - col += 9; - dprint(LINE_CPU+5, col, fsb, 3,0); - col += 3; - cprint(LINE_CPU+5, col +1, "MHz"); - col += 4; - } + print_cpu_line(dramclock, fsb, 2); } static void poll_fsb_p4(void) { ulong fsb, idetect; float coef = getP4PMmultiplier(); + char *name; + int col,temp; fsb = ((extclock /1000) / coef); - /* Print FSB */ - cprint(LINE_CPU+5, col +1, "/ FSB : "); - col += 9; - dprint(LINE_CPU+5, col, fsb, 3,0); - col += 3; - cprint(LINE_CPU+5, col +1, "MHz"); - col += 4; - /* For synchro only chipsets */ pci_conf_read( 0, 0, 0, 0x02, 2, &idetect); - if (idetect == 0x2540 || idetect == 0x254C) { - print_fsb_info(fsb, "RAM : ", "DDR"); + if (idetect == 0x2540 || idetect == 0x254C) + { + print_cpu_line(fsb, fsb, 1); + } else { + /* Print the controller name */ + col = COL_SPEC; + cprint(LINE_CPU, col, "Chipset: "); + col += 9; + /* Print the controller name */ + name = controllers[ctrl.index].name; + cprint(LINE_CPU, col, name); + /* Now figure out how much I just printed */ + temp = 20; + while(name[temp - 20] != '\0') { + col++; + temp++; + } + + if(temp < 36){ + cprint(LINE_CPU, col +1, "- FSB : "); + col += 9; + dprint(LINE_CPU, col, fsb, 3,0); + col += 3; + } + } } @@ -2029,7 +2437,7 @@ static void poll_fsb_i855(void) { double dramclock, dramratio, fsb ; unsigned int msr_lo, msr_hi; - ulong mchcfg, centri, idetect; + ulong mchcfg, idetect; int coef; pci_conf_read( 0, 0, 0, 0x02, 2, &idetect); @@ -2037,33 +2445,16 @@ static void poll_fsb_i855(void) { /* Find multiplier (by MSR) */ /* Is it a Pentium M ? */ - if (cpu_id.type == 6) { + if (cpu_id.vers.bits.family == 6) { rdmsr(0x2A, msr_lo, msr_hi); coef = (msr_lo >> 22) & 0x1F; - - /* Is it an i855GM or PM ? */ - if (idetect == 0x3580) { - cprint(LINE_CPU+5, col-1, "i855GM/GME "); - col += 10; - } } else { rdmsr(0x2C, msr_lo, msr_hi); coef = (msr_lo >> 24) & 0x1F; - cprint(LINE_CPU+5, col-1, "i852PM/GM "); - col += 9; } fsb = ((extclock /1000) / coef); - /* Print FSB */ - cprint(LINE_CPU+5, col, "/ FSB : "); col += 8; - dprint(LINE_CPU+5, col, fsb, 3,0); col += 3; - cprint(LINE_CPU+5, col +1, "MHz"); col += 4; - - /* Is it a Centrino platform or only an i855 platform ? */ - pci_conf_read( 2, 2, 0, 0x02, 2, ¢ri); - if (centri == 0x1043) { cprint(LINE_CPU+5, col +1, "/ Centrino Mobile Platform"); } - else { cprint(LINE_CPU+5, col +1, "/ Mobile Platform"); } /* Compute DRAM Clock */ @@ -2088,7 +2479,7 @@ static void poll_fsb_i855(void) { dramclock = fsb * dramratio; /* ...and print */ - print_fsb_info(dramclock, "RAM : ", "DDR"); + print_cpu_line(dramclock, fsb, 1); } @@ -2099,6 +2490,8 @@ static void poll_fsb_amd32(void) { unsigned long temp; double dramclock; double coef2; + int col; + char *name; /* First, got the FID */ rdmsr(0x0c0010015, mcgsrl, mcgsth); @@ -2112,8 +2505,27 @@ static void poll_fsb_amd32(void) { /* Compute the final FSB Clock */ dramclock = (extclock /1000) / coef2; - /* ...and print */ - print_fsb_info(dramclock, "FSB : ", "DDR"); + /* Print the controller name */ + col = COL_SPEC; + cprint(LINE_CPU, col, "Chipset: "); + col += 9; + /* Print the controller name */ + name = controllers[ctrl.index].name; + cprint(LINE_CPU, col, name); + /* Now figure out how much I just printed */ + temp = 20; + while(name[temp - 20] != '\0') { + col++; + temp++; + } + + if(temp < 36){ + cprint(LINE_CPU, col +1, "- FSB : "); + col += 9; + dprint(LINE_CPU, col, dramclock, 3,0); + col += 3; + } + } @@ -2151,20 +2563,13 @@ static void poll_fsb_nf2(void) { fsb = ((extclock /1000) / coef); /* ...and print */ - - cprint(LINE_CPU+5, col, "/ FSB : "); - col += 8; - dprint(LINE_CPU+5, col, fsb, 3,0); - col += 3; - cprint(LINE_CPU+5, col +1, "MHz"); - - print_fsb_info(dramclock, "RAM : ", "DDR"); + print_cpu_line(dramclock, fsb, 1); } static void poll_fsb_us15w(void) { - double dramclock, dramratio, fsb, gfx; + double dramclock, dramratio, fsb; unsigned long msr; /* Find dramratio */ @@ -2181,7 +2586,8 @@ static void poll_fsb_us15w(void) { } else { fsb = 400; } - + +/* switch (( msr >> 0 ) & 7) { case 0: gfx = 100; @@ -2205,48 +2611,29 @@ static void poll_fsb_us15w(void) { gfx = 0; break; } + */ dramclock = fsb * dramratio; // Print DRAM Freq - print_fsb_info(dramclock, "RAM : ", "DDR"); - - /* Print FSB (only if ECC is not enabled) */ - cprint(LINE_CPU+4, col +1, "- FSB : "); - col += 9; - dprint(LINE_CPU+4, col, fsb, 3,0); - col += 3; - cprint(LINE_CPU+4, col +1, "MHz"); - col += 4; - - cprint(LINE_CPU+4, col +1, "- GFX : "); - col += 9; - dprint(LINE_CPU+4, col, gfx, 3,0); - col += 3; - cprint(LINE_CPU+4, col +1, "MHz"); - col += 4; + print_cpu_line(dramclock, fsb, 1); } static void poll_fsb_nhm(void) { double dramclock, dramratio, fsb; - unsigned long mc_dimm_clk_ratio, qpi_pll_status; + unsigned long mc_dimm_clk_ratio; float coef = getNHMmultiplier(); - float qpi_speed; + //unsigned long qpi_pll_status; + //float qpi_speed; - fsb = ((extclock /1000) / coef); - /* Print FSB */ - cprint(LINE_CPU+5, col +1, "/ BCLK : "); - col += 10; - dprint(LINE_CPU+5, col, fsb, 3,0); - col += 3; - cprint(LINE_CPU+5, col +1, "MHz"); - col += 4; + fsb = ((extclock /1000) / coef); /* Print QPI Speed (if ECC not supported) */ - if(ctrl.mode == ECC_NONE && cpu_id.model == 10) { + /* + if(ctrl.mode == ECC_NONE && cpu_id.vers.bits.model == 10) { pci_conf_read(nhm_bus, 2, 1, 0x50, 2, &qpi_pll_status); qpi_speed = (qpi_pll_status & 0x7F) * ((extclock / 1000) / coef) * 2; cprint(LINE_CPU+5, col +1, "/ QPI : "); @@ -2261,6 +2648,7 @@ static void poll_fsb_nhm(void) { cprint(LINE_CPU+5, col +1, "GT/s"); col += 5; } + */ /* Get the clock ratio */ @@ -2272,29 +2660,23 @@ static void poll_fsb_nhm(void) { dramclock = fsb * dramratio / 2; // Print DRAM Freq - print_fsb_info(dramclock, "RAM : ", "DDR3-"); + print_cpu_line(dramclock, fsb, 3); } static void poll_fsb_nhm32(void) { double dramclock, dramratio, fsb; - unsigned long mc_dimm_clk_ratio, qpi_pll_status; + unsigned long mc_dimm_clk_ratio; float coef = getNHMmultiplier(); - float qpi_speed; + //unsigned long qpi_pll_status; + //float qpi_speed; fsb = ((extclock /1000) / coef); - /* Print FSB */ - cprint(LINE_CPU+5, col +1, "/ BCLK : "); - col += 10; - dprint(LINE_CPU+5, col, fsb, 3,0); - col += 3; - cprint(LINE_CPU+5, col +1, "MHz"); - col += 4; - /* Print QPI Speed (if ECC not supported) */ - if(ctrl.mode == ECC_NONE && cpu_id.model == 12) { + /* + if(ctrl.mode == ECC_NONE && cpu_id.vers.bits.model == 12) { pci_conf_read(nhm_bus, 2, 1, 0x50, 2, &qpi_pll_status); qpi_speed = (qpi_pll_status & 0x7F) * ((extclock / 1000) / coef) * 2; cprint(LINE_CPU+5, col +1, "/ QPI : "); @@ -2309,6 +2691,7 @@ static void poll_fsb_nhm32(void) { cprint(LINE_CPU+5, col +1, "GT/s"); col += 5; } + */ /* Get the clock ratio */ @@ -2320,41 +2703,23 @@ static void poll_fsb_nhm32(void) { dramclock = fsb * dramratio / 2; // Print DRAM Freq - print_fsb_info(dramclock, "RAM : ", "DDR3-"); + print_cpu_line(dramclock, fsb, 3); } static void poll_fsb_wmr(void) { double dramclock, dramratio, fsb; - unsigned long dev0, mchcfg; + unsigned long dev0; float coef = getNHMmultiplier(); long *ptr; fsb = ((extclock / 1000) / coef); - if(ctrl.mode == ECC_NONE) - { - col = 0; - cprint(LINE_CPU+5, col, "IMC : "); col += 6; - getIntelPNS(); - //cprint(LINE_CPU+5, col, "(ECC : Disabled)"); - //col += 16; - } - - /* Print FSB */ - cprint(LINE_CPU+5, col +1, "/ BCLK : "); - col += 10; - dprint(LINE_CPU+5, col, fsb, 3,0); - col += 3; - cprint(LINE_CPU+5, col +1, "MHz"); - col += 4; - /* Find dramratio */ pci_conf_read( 0, 0, 0, 0x48, 4, &dev0); dev0 &= 0xFFFFC000; ptr=(long*)(dev0+0x2C20); - mchcfg = *ptr & 0xFFFF; dramratio = 1; /* Get the clock ratio */ @@ -2364,35 +2729,44 @@ static void poll_fsb_wmr(void) { dramclock = fsb * dramratio; // Print DRAM Freq - print_fsb_info(dramclock, "RAM : ", "DDR3-"); + print_cpu_line(dramclock, fsb, 3); } static void poll_fsb_snb(void) { double dramclock, dramratio, fsb; - unsigned long dev0, mchcfg; + unsigned long dev0; float coef = getSNBmultiplier(); long *ptr; fsb = ((extclock / 1000) / coef); - if(ctrl.mode == ECC_NONE) - { - col = 0; - cprint(LINE_CPU+5, col, "IMC : "); col += 6; - getIntelPNS(); - //cprint(LINE_CPU+5, col, "(ECC : Disabled)"); - //col += 16; - } + /* Find dramratio */ + pci_conf_read( 0, 0, 0, 0x48, 4, &dev0); + dev0 &= 0xFFFFC000; + ptr=(long*)(dev0+0x5E04); + dramratio = 1; + + /* Get the clock ratio */ + dramratio = (float)(*ptr & 0x1F) * (133.34f / 100.0f); + + // Compute RAM Frequency + dramclock = fsb * dramratio; - /* Print FSB */ - cprint(LINE_CPU+5, col +1, "/ BCLK : "); - col += 10; - dprint(LINE_CPU+5, col, fsb, 3,0); - col += 3; - cprint(LINE_CPU+5, col +1, "MHz"); - col += 4; + // Print DRAM Freq + print_cpu_line(dramclock, fsb, 3); + +} + +static void poll_fsb_ivb(void) { + + double dramclock, dramratio, fsb; + unsigned long dev0, mchcfg; + float coef = getSNBmultiplier(); + long *ptr; + + fsb = ((extclock / 1000) / coef); /* Find dramratio */ pci_conf_read( 0, 0, 0, 0x48, 4, &dev0); @@ -2402,13 +2776,47 @@ static void poll_fsb_snb(void) { dramratio = 1; /* Get the clock ratio */ - dramratio = (float)(*ptr & 0x1F) * (133.34f / 100.0f); + switch((mchcfg >> 8) & 0x01) + { + case 0x0: + dramratio = (float)(*ptr & 0x1F) * (133.34f / 100.0f); + break; + case 0x1: + dramratio = (float)(*ptr & 0x1F) * (100.0f / 100.0f); + break; + } + + // Compute RAM Frequency + dramclock = fsb * dramratio; + + // Print DRAM Freq + print_cpu_line(dramclock, fsb, 3); + +} + +static void poll_fsb_snbe(void) { + + double dramclock, dramratio, fsb; + unsigned long dev0; + float coef = getSNBmultiplier(); + + fsb = ((extclock / 1000) / coef); + + /* Find dramratio */ + pci_conf_read( 0xFF, 10, 1, 0x98, 4, &dev0); + dev0 &= 0xFFFFFFFF; + dramratio = 1; + + /* Get the clock ratio */ + dramratio = (float)(dev0 & 0x3F) * (66.67f / 100.0f); // Compute RAM Frequency dramclock = fsb * dramratio; // Print DRAM Freq - print_fsb_info(dramclock, "RAM : ", "DDR3-"); + print_cpu_line(dramclock, fsb, 3); + + } @@ -2419,9 +2827,7 @@ static void poll_timings_nf4ie(void) { ulong regd0, reg8c, reg9c, reg80; - int cas, rcd, rp, ras; - - cprint(LINE_CPU+5, col +1, "- Type : DDR-II"); + int cas, rcd, rp, ras, chan; //Now, read Registers pci_conf_read( 0, 1, 1, 0xD0, 4, ®d0); @@ -2435,14 +2841,12 @@ static void poll_timings_nf4ie(void) { rp = (reg9c >> 8) & 0xF; ras = (reg8c >> 16) & 0x3F; - print_timings_info(cas, rcd, rp, ras); - if (reg80 & 0x3) { - cprint(LINE_CPU+6, col2, "/ Dual Channel (128 bits)"); + chan = 2; } else { - cprint(LINE_CPU+6, col2, "/ Single Channel (64 bits)"); + chan = 1; } - + print_ram_line(cas, rcd, rp, ras, chan); } static void poll_timings_i875(void) { @@ -2450,24 +2854,16 @@ static void poll_timings_i875(void) { ulong dev6, dev62; ulong temp; float cas; - int rcd, rp, ras; + int rcd, rp, ras, chan; long *ptr, *ptr2; - /* Read the MMR Base Address & Define the pointer */ - pci_conf_read( 0, 6, 0, 0x10, 4, &dev6); - - /* Now, the PAT ritual ! (Kant and Luciano will love this) */ pci_conf_read( 0, 6, 0, 0x40, 4, &dev62); ptr2=(long*)(dev6+0x68); - if ((dev62&0x3) == 0 && ((*ptr2 >> 14)&1) == 1) { - cprint(LINE_CPU+5, col +1, "- PAT : Enabled"); - } else { - cprint(LINE_CPU+5, col +1, "- PAT : Disabled"); - } + /* Read the MMR Base Address & Define the pointer */ + pci_conf_read( 0, 6, 0, 0x10, 4, &dev6); /* Now, we could check some additionnals timings infos) */ - ptr=(long*)(dev6+0x60); // CAS Latency (tCAS) temp = ((*ptr >> 5)& 0x3); @@ -2485,20 +2881,20 @@ static void poll_timings_i875(void) { temp = ((*ptr >> 7)& 0x7); ras = 10 - temp; - // Print timings - print_timings_info(cas, rcd, rp, ras); - // Print 64 or 128 bits mode if (((*ptr2 >> 21)&3) > 0) { - cprint(LINE_CPU+6, col2, "/ Dual Channel (128 bits)"); + chan = 2; } else { - cprint(LINE_CPU+6, col2, "/ Single Channel (64 bits)"); + chan = 1; } + print_ram_line(cas, rcd, rp, ras, chan); } static void poll_timings_i925(void) { // Thanks for CDH optis + float cas; + int rcd,rp,ras,chan; ulong dev0, drt, drc, dcc, idetect, temp; long *ptr; @@ -2519,69 +2915,53 @@ static void poll_timings_i925(void) { ptr=(long*)(dev0+0x200); dcc = *ptr & 0xFFFFFFFF; - //Determine DDR or DDR-II - if ((drc & 3) == 2) { - cprint(LINE_CPU+5, col +1, "- Type : DDR2"); - } else { - cprint(LINE_CPU+5, col +1, "- Type : DDR1"); - } - - // Now, detect timings - cprint(LINE_CPU+6, col2 +1, "/ CAS : "); - col2 += 9; - // CAS Latency (tCAS) temp = ((drt >> 8)& 0x3); if ((drc & 3) == 2){ // Timings DDR-II - if (temp == 0x0) { cprint(LINE_CPU+6, col2, "5-"); } - else if (temp == 0x1) { cprint(LINE_CPU+6, col2, "4-"); } - else if (temp == 0x2) { cprint(LINE_CPU+6, col2, "3-"); } - else { cprint(LINE_CPU+6, col2, "6-"); } + if (temp == 0x0) { cas = 5; } + else if (temp == 0x1) { cas = 4; } + else if (temp == 0x2) { cas = 3; } + else { cas = 6; } } else { // Timings DDR-I - if (temp == 0x0) { cprint(LINE_CPU+6, col2, "3-"); } - else if (temp == 0x1) { cprint(LINE_CPU+6, col2, "2.5-"); col2 +=2;} - else { cprint(LINE_CPU+6, col2, "2-"); } + if (temp == 0x0) { cas = 3; } + else if (temp == 0x1) { cas = 2.5f;} + else { cas = 2; } } - col2 +=2; // RAS-To-CAS (tRCD) - dprint(LINE_CPU+6, col2, ((drt >> 4)& 0x3)+2, 1 ,0); - cprint(LINE_CPU+6, col2+1, "-"); - col2 +=2; + rcd = ((drt >> 4)& 0x3)+2; // RAS Precharge (tRP) - dprint(LINE_CPU+6, col2, (drt&0x3)+2, 1 ,0); - cprint(LINE_CPU+6, col2+1, "-"); - col2 +=2; + rp = (drt&0x3)+2; // RAS Active to precharge (tRAS) // If Lakeport, than change tRAS computation (Thanks to CDH, again) if (idetect > 0x2700) - temp = ((drt >> 19)& 0x1F); + ras = ((drt >> 19)& 0x1F); else - temp = ((drt >> 20)& 0x0F); + ras = ((drt >> 20)& 0x0F); - dprint(LINE_CPU+6, col2, temp , 1 ,0); - (temp < 10)?(col2 += 1):(col2 += 2); - - cprint(LINE_CPU+6, col2+1, "/"); col2 +=2; temp = (dcc&0x3); - if (temp == 1) { cprint(LINE_CPU+6, col2, " Dual Channel (Asymmetric)"); } - else if (temp == 2) { cprint(LINE_CPU+6, col2, " Dual Channel (Interleaved)"); } - else { cprint(LINE_CPU+6, col2, " Single Channel (64 bits)"); } + if (temp == 1) { chan = 2; } + else if (temp == 2) { chan = 2; } + else { chan = 1; } + + print_ram_line(cas, rcd, rp, ras, chan); } static void poll_timings_i965(void) { // Thanks for CDH optis - ulong dev0, temp, c0ckectrl, c1ckectrl, offset; - ulong ODT_Control_Register, Precharge_Register, ACT_Register, Read_Register, Misc_Register; + ulong dev0, c0ckectrl, c1ckectrl, offset; + ulong ODT_Control_Register, Precharge_Register, ACT_Register, Read_Register; long *ptr; + int rcd,rp,ras,chan; + float cas; //Now, read MMR Base Address pci_conf_read( 0, 0, 0, 0x48, 4, &dev0); @@ -2608,56 +2988,37 @@ static void poll_timings_i965(void) { ptr = (long*)(dev0+offset+0x258); Read_Register = *ptr & 0xFFFFFFFF; - ptr = (long*)(dev0+offset+0x244); - Misc_Register = *ptr & 0xFFFFFFFF; - - //Intel 965 Series only support DDR2 - cprint(LINE_CPU+5, col +1, "- Type : DDR-II"); - - // Now, detect timings - cprint(LINE_CPU+6, col2 +1, "/ CAS : "); - col2 += 9; // CAS Latency (tCAS) - temp = ((ODT_Control_Register >> 17)& 7) + 3.0f; - dprint(LINE_CPU+6, col2, temp, 1 ,0); - cprint(LINE_CPU+6, col2+1, "-"); - (temp < 10)?(col2 += 2):(col2 += 3); + cas = ((ODT_Control_Register >> 17)& 7) + 3.0f; // RAS-To-CAS (tRCD) - temp = (Read_Register >> 16) & 0xF; - dprint(LINE_CPU+6, col2, temp, 1 ,0); - cprint(LINE_CPU+6, col2+1, "-"); - (temp < 10)?(col2 += 2):(col2 += 3); + rcd = (Read_Register >> 16) & 0xF; // RAS Precharge (tRP) - temp = (ACT_Register >> 13) & 0xF; - dprint(LINE_CPU+6, col2, temp, 1 ,0); - cprint(LINE_CPU+6, col2+1, "-"); - (temp < 10)?(col2 += 2):(col2 += 3); + rp = (ACT_Register >> 13) & 0xF; // RAS Active to precharge (tRAS) - temp = (Precharge_Register >> 11) & 0x1F; - dprint(LINE_CPU+6, col2, temp, 1 ,0); - (temp < 10)?(col2 += 1):(col2 += 2); - - cprint(LINE_CPU+6, col2+1, "/"); col2 +=2; + ras = (Precharge_Register >> 11) & 0x1F; if ((c0ckectrl >> 20 & 0xF) && (c1ckectrl >> 20 & 0xF)) { - cprint(LINE_CPU+6, col2+1, "Dual Channel"); + chan = 2; } else { - cprint(LINE_CPU+6, col2+1, "Single Channel"); + chan = 1; } + print_ram_line(cas, rcd, rp, ras, chan); } static void poll_timings_im965(void) { // Thanks for CDH optis - ulong dev0, temp, c0ckectrl, c1ckectrl, offset; + ulong dev0, c0ckectrl, c1ckectrl, offset; ulong ODT_Control_Register, Precharge_Register; long *ptr; - + int rcd,rp,ras,chan; + float cas; + //Now, read MMR Base Address pci_conf_read( 0, 0, 0, 0x48, 4, &dev0); dev0 &= 0xFFFFC000; @@ -2677,55 +3038,36 @@ static void poll_timings_im965(void) { ptr = (long*)(dev0+offset+0x1214); Precharge_Register = *ptr & 0xFFFFFFFF; - //Intel 965 Series only support DDR2 - cprint(LINE_CPU+5, col+1, "- Type : DDR-II"); - - // Now, detect timings - cprint(LINE_CPU+6, col2 +1, "/ CAS : "); - col2 += 9; - // CAS Latency (tCAS) - temp = ((ODT_Control_Register >> 23)& 7) + 3.0f; - dprint(LINE_CPU+6, col2, temp, 1 ,0); - cprint(LINE_CPU+6, col2+1, "-"); - (temp < 10)?(col2 += 2):(col2 += 3); + cas = ((ODT_Control_Register >> 23)& 7) + 3.0f; // RAS-To-CAS (tRCD) - temp = ((Precharge_Register >> 5)& 7) + 2.0f; - dprint(LINE_CPU+6, col2, temp, 1 ,0); - cprint(LINE_CPU+6, col2+1, "-"); - (temp < 10)?(col2 += 2):(col2 += 3); + rcd = ((Precharge_Register >> 5)& 7) + 2.0f; // RAS Precharge (tRP) - temp = (Precharge_Register & 7) + 2.0f; - dprint(LINE_CPU+6, col2, temp, 1 ,0); - cprint(LINE_CPU+6, col2+1, "-"); - (temp < 10)?(col2 += 2):(col2 += 3); + rp = (Precharge_Register & 7) + 2.0f; // RAS Active to precharge (tRAS) - temp = (Precharge_Register >> 21) & 0x1F; - dprint(LINE_CPU+6, col2, temp, 1 ,0); - (temp < 10)?(col2 += 1):(col2 += 2); + ras = (Precharge_Register >> 21) & 0x1F; - cprint(LINE_CPU+6, col2+1, "/"); col2 +=2; if ((c0ckectrl >> 20 & 0xF) && (c1ckectrl >> 20 & 0xF)) { - cprint(LINE_CPU+6, col2+1, "Dual Channel"); + chan = 2; } else { - cprint(LINE_CPU+6, col2+1, "Single Channel"); + chan = 1; } - + print_ram_line(cas, rcd, rp, ras, chan); } static void poll_timings_p35(void) { // Thanks for CDH optis float cas; - int rcd, rp, ras; - ulong dev0, Device_ID, Memory_Check, c0ckectrl, c1ckectrl, offset; - ulong ODT_Control_Register, Precharge_Register, ACT_Register, Read_Register, Misc_Register; + int rcd, rp, ras, chan; + ulong dev0, Device_ID, c0ckectrl, c1ckectrl, offset; + ulong ODT_Control_Register, Precharge_Register, ACT_Register, Read_Register; long *ptr; - + pci_conf_read( 0, 0, 0, 0x02, 2, &Device_ID); Device_ID &= 0xFFFF; @@ -2754,30 +3096,9 @@ static void poll_timings_p35(void) { ptr = (long*)(dev0+offset+0x258); Read_Register = *ptr & 0xFFFFFFFF; - ptr = (long*)(dev0+offset+0x244); - Misc_Register = *ptr & 0xFFFFFFFF; - - // On P45, check 1A8 - if(Device_ID > 0x2E00) { - ptr = (long*)(dev0+offset+0x1A8); - Memory_Check = *ptr & 0xFFFFFFFF; - Memory_Check >>= 2; - Memory_Check &= 1; - Memory_Check = !Memory_Check; - } else { - ptr = (long*)(dev0+offset+0x1E8); - Memory_Check = *ptr & 0xFFFFFFFF; - } - - //Determine DDR-II or DDR-III - if (Memory_Check & 1) { - cprint(LINE_CPU+5, col +1, "- Type : DDR2"); - } else { - cprint(LINE_CPU+5, col +1, "- Type : DDR3"); - } // CAS Latency (tCAS) - if(Device_ID > 0x2E00) { + if(Device_ID > 0x2E00 && imc_type != 8) { cas = ((ODT_Control_Register >> 8)& 0x3F) - 6.0f; } else { cas = ((ODT_Control_Register >> 8)& 0x3F) - 9.0f; @@ -2792,22 +3113,18 @@ static void poll_timings_p35(void) { // RAS Active to precharge (tRAS) ras = Precharge_Register & 0x3F; - print_timings_info(cas, rcd, rp, ras); - - cprint(LINE_CPU+6, col2+1, "/"); col2 +=2; - if ((c0ckectrl >> 20 & 0xF) && (c1ckectrl >> 20 & 0xF)) { - cprint(LINE_CPU+6, col2+1, "Dual Channel"); + chan = 2; } else { - cprint(LINE_CPU+6, col2+1, "Single Channel"); + chan = 1; } - + print_ram_line(cas, rcd, rp, ras, chan); } static void poll_timings_wmr(void) { float cas; - int rcd, rp, ras; + int rcd, rp, ras, chan; ulong dev0, c0ckectrl, c1ckectrl, offset; ulong ODT_Control_Register, Precharge_Register, ACT_Register, Read_Register, MRC_Register; long *ptr; @@ -2856,22 +3173,20 @@ static void poll_timings_wmr(void) { // RAS Active to precharge (tRAS) ras = Precharge_Register & 0x3F; - print_timings_info(cas, rcd, rp, ras); - - cprint(LINE_CPU+6, col2+1, "/"); col2 +=2; - if ((c0ckectrl >> 20 & 0xF) && (c1ckectrl >> 20 & 0xF)) { - cprint(LINE_CPU+6, col2+1, "Dual Channel"); + chan = 2; } else { - cprint(LINE_CPU+6, col2+1, "Single Channel"); + chan = 1; } + print_ram_line(cas, rcd, rp, ras, chan); + } static void poll_timings_snb(void) { float cas; - int rcd, rp, ras; + int rcd, rp, ras, chan; ulong dev0, offset; ulong IMC_Register, MCMain0_Register, MCMain1_Register; long *ptr; @@ -2897,30 +3212,127 @@ static void poll_timings_snb(void) { // RAS Active to precharge (tRAS) ras = (IMC_Register >> 16) & 0xFF; - print_timings_info(cas, rcd, rp, ras); + // Channels + ptr = (long*)(dev0+offset+0x5004); + MCMain0_Register = *ptr & 0xFFFF; + ptr = (long*)(dev0+offset+0x5008); + MCMain1_Register = *ptr & 0xFFFF; + + if(MCMain0_Register == 0 || MCMain1_Register == 0) { + chan = 1; + } else { + chan = 2; + } + + print_ram_line(cas, rcd, rp, ras, chan); +} - cprint(LINE_CPU+6, col2+1, "/"); col2 +=2; +static void poll_timings_hsw(void) { + + float cas; + int rcd, rp, ras, chan; + ulong dev0, offset = 0; + ulong IMC_Register, MCMain0_Register, MCMain1_Register; + long *ptr; + + //Now, read MMR Base Address + pci_conf_read( 0, 0, 0, 0x48, 4, &dev0); + dev0 &= 0xFFFFC000; // Channels ptr = (long*)(dev0+offset+0x5004); MCMain0_Register = *ptr & 0xFFFF; + ptr = (long*)(dev0+offset+0x5008); MCMain1_Register = *ptr & 0xFFFF; - if(MCMain0_Register == 0 || MCMain1_Register == 0) { - cprint(LINE_CPU+6, col2+1, "Single Channel"); + if(MCMain0_Register && MCMain1_Register) { + chan = 2; } else { - cprint(LINE_CPU+6, col2+1, "Dual Channel"); + chan = 1; } + + if(MCMain0_Register) { offset = 0x0000; } else { offset = 0x0400; } + + // CAS Latency (tCAS) + ptr = (long*)(dev0+offset+0x4014); + IMC_Register = *ptr & 0xFFFFFFFF; + cas = (float)(IMC_Register & 0x1F); + + ptr = (long*)(dev0+offset+0x4000); + IMC_Register = *ptr & 0xFFFFFFFF; + + // RAS-To-CAS (tRCD) + rcd = IMC_Register & 0x1F; + + // RAS Precharge (tRP) + rp = (IMC_Register >> 5) & 0x1F; + + // RAS Active to precharge (tRAS) + ras = (IMC_Register >> 10) & 0x3F; + + + print_ram_line(cas, rcd, rp, ras, chan); +} + +static void poll_timings_snbe(void) { + + float cas; + int rcd, rp, ras; + int nb_channel = 0, current_channel = 0; + ulong temp, IMC_Register; + long *ptr; + + //Read Channel #1 + pci_conf_read(0xFF, 16, 2, 0x80, 4, &temp); + temp &= 0x3F; + if(temp != 0xB) { current_channel = 0; nb_channel++; } + + //Read Channel #2 + pci_conf_read(0xFF, 16, 3, 0x80, 4, &temp); + temp &= 0x3F; + if(temp != 0xB) { current_channel = 1; nb_channel++; } + + //Read Channel #3 + pci_conf_read(0xFF, 16, 6, 0x80, 4, &temp); + temp &= 0x3F; + if(temp != 0xB) { current_channel = 4; nb_channel++; } + + //Read Channel #4 + pci_conf_read(0xFF, 16, 7, 0x80, 4, &temp); + temp &= 0x3F; + if(temp != 0xB) { current_channel = 5; nb_channel++; } + + + pci_conf_read(0, 5, 0, 0x84, 4, &temp); + ptr = (long*)((temp & 0xFC000000) + (MAKE_PCIE_ADDRESS(0xFF,16,current_channel) | 0x200)); + IMC_Register = *ptr & 0xFFFFFFFF; + + // CAS Latency (tCAS) + cas = (float)((IMC_Register >> 9) & 0x1F); + + // RAS-To-CAS (tRCD) + rcd = IMC_Register & 0x1F; + + // RAS Precharge (tRP) + rp = (IMC_Register >> 5) & 0x0F; + + // RAS Active to precharge (tRAS) + ras = (IMC_Register >> 19) & 0x3F; + + + print_ram_line(cas, rcd, rp, ras, nb_channel); } static void poll_timings_5400(void) { // Thanks for CDH optis - ulong ambase, mtr1, mtr2, offset, mca, temp; + ulong ambase, mtr1, mtr2, offset, mca; long *ptr; - + float cas; + int rcd, rp, ras, chan; + //Hard-coded Ambase value (should not be realocated by software when using Memtest86+ ambase = 0xFE000000; offset = mtr1 = mtr2 = 0; @@ -2942,49 +3354,36 @@ static void poll_timings_5400(void) { //cprint(LINE_CPU+5, col +1, "- Type : FBD"); // Now, detect timings - cprint(LINE_CPU+6, col2 +1, "/ CAS : "); - col2 += 9; // CAS Latency (tCAS) - temp = mtr2 & 0xF; - dprint(LINE_CPU+6, col2, temp, 1 ,0); - cprint(LINE_CPU+6, col2+1, "-"); - col2 += 2; + cas = mtr2 & 0xF; // RAS-To-CAS (tRCD) - temp = 6 - ((mtr1 >> 10) & 3); - dprint(LINE_CPU+6, col2, temp, 1 ,0); - cprint(LINE_CPU+6, col2+1, "-"); - col2 += 2; + rcd = 6 - ((mtr1 >> 10) & 3); // RAS Precharge (tRP) - temp = 6 - ((mtr1 >> 8) & 3); - dprint(LINE_CPU+6, col2, temp, 1 ,0); - cprint(LINE_CPU+6, col2+1, "-"); - col2 += 2; + rp = 6 - ((mtr1 >> 8) & 3); // RAS Active to precharge (tRAS) - temp = 16 - (3 * ((mtr1 >> 29) & 3)) + ((mtr1 >> 12) & 3); - if(((mtr1 >> 12) & 3) == 3 && ((mtr1 >> 29) & 3) == 2) { temp = 9; } - - dprint(LINE_CPU+6, col2, temp, 1 ,0); - (temp < 10)?(col2 += 1):(col2 += 2); + ras = 16 - (3 * ((mtr1 >> 29) & 3)) + ((mtr1 >> 12) & 3); + if(((mtr1 >> 12) & 3) == 3 && ((mtr1 >> 29) & 3) == 2) { ras = 9; } - cprint(LINE_CPU+6, col2+1, "/"); col2 +=2; if ((mca >> 14) & 1) { - cprint(LINE_CPU+6, col2+1, "Single Channel"); + chan = 1; } else { - cprint(LINE_CPU+6, col2+1, "Dual Channel"); + chan = 2; } + print_ram_line(cas, rcd, rp, ras, chan); + } static void poll_timings_E7520(void) { ulong drt, ddrcsr; float cas; - int rcd, rp, ras; + int rcd, rp, ras, chan; pci_conf_read( 0, 0, 0, 0x78, 4, &drt); pci_conf_read( 0, 0, 0, 0x9A, 2, &ddrcsr); @@ -2993,21 +3392,23 @@ static void poll_timings_E7520(void) { rcd = ((drt >> 10) & 1) + 3; rp = ((drt >> 9) & 1) + 3; ras = ((drt >> 14) & 3) + 11; - - print_timings_info(cas, rcd, rp, ras); if ((ddrcsr & 0xF) >= 0xC) { - cprint(LINE_CPU+6, col2, "/ Dual Channel (128 bits)"); + chan = 2; } else { - cprint(LINE_CPU+6, col2, "/ Single Channel (64 bits)"); + chan = 1; } + + print_ram_line(cas, rcd, rp, ras, chan); } static void poll_timings_i855(void) { ulong drt, temp; - + float cas; + int rcd, rp, ras; + pci_conf_read( 0, 0, 0, 0x78, 4, &drt); /* Now, we could print some additionnals timings infos) */ @@ -3016,27 +3417,26 @@ static void poll_timings_i855(void) { // CAS Latency (tCAS) temp = ((drt >> 4)&0x1); - if (temp == 0x0) { cprint(LINE_CPU+6, col2, "2.5-"); col2 += 4; } - else { cprint(LINE_CPU+6, col2, "2-"); col2 +=2; } + if (temp == 0x0) { cas = 2.5; } + else { cas = 2; } // RAS-To-CAS (tRCD) temp = ((drt >> 2)& 0x1); - if (temp == 0x0) { cprint(LINE_CPU+6, col2, "3-"); } - else { cprint(LINE_CPU+6, col2, "2-"); } - col2 +=2; + if (temp == 0x0) { rcd = 3; } + else { rcd = 2; } // RAS Precharge (tRP) temp = (drt&0x1); - if (temp == 0x0) { cprint(LINE_CPU+6, col2, "3-"); } - else { cprint(LINE_CPU+6, col2, "2-"); } - col2 +=2; + if (temp == 0x0) { rp = 3 ; } + else { rp = 2; } // RAS Active to precharge (tRAS) temp = 7-((drt >> 9)& 0x3); - if (temp == 0x0) { cprint(LINE_CPU+6, col2, "7"); } - if (temp == 0x1) { cprint(LINE_CPU+6, col2, "6"); } - if (temp == 0x2) { cprint(LINE_CPU+6, col2, "5"); } - col2 +=1; + if (temp == 0x0) { ras = 7; } + if (temp == 0x1) { ras = 6; } + if (temp == 0x2) { ras = 5; } + + print_ram_line(cas, rcd, rp, ras, 1); } @@ -3044,7 +3444,7 @@ static void poll_timings_E750x(void) { ulong drt, drc, temp; float cas; - int rcd, rp, ras; + int rcd, rp, ras, chan; pci_conf_read( 0, 0, 0, 0x78, 4, &drt); pci_conf_read( 0, 0, 0, 0x7C, 4, &drc); @@ -3056,20 +3456,22 @@ static void poll_timings_E750x(void) { temp = ((drt >> 9) & 3); if (temp == 2) { ras = 5; } else if (temp == 1) { ras = 6; } else { ras = 7; } - print_timings_info(cas, rcd, rp, ras); - if (((drc >> 22)&1) == 1) { - cprint(LINE_CPU+6, col2, "/ Dual Channel (128 bits)"); + chan = 2; } else { - cprint(LINE_CPU+6, col2, "/ Single Channel (64 bits)"); + chan = 1; } + print_ram_line(cas, rcd, rp, ras, chan); + } static void poll_timings_i852(void) { ulong drt, temp; - + float cas; + int rcd, rp, ras; + pci_conf_read( 0, 0, 1, 0x60, 4, &drt); /* Now, we could print some additionnals timings infos) */ @@ -3078,80 +3480,62 @@ static void poll_timings_i852(void) { // CAS Latency (tCAS) temp = ((drt >> 5)&0x1); - if (temp == 0x0) { cprint(LINE_CPU+6, col2, "2.5-"); col2 += 4; } - else { cprint(LINE_CPU+6, col2, "2-"); col2 +=2; } + if (temp == 0x0) { cas = 2.5; } + else { cas = 2; } // RAS-To-CAS (tRCD) temp = ((drt >> 2)& 0x3); - if (temp == 0x0) { cprint(LINE_CPU+6, col2, "4-"); } - if (temp == 0x1) { cprint(LINE_CPU+6, col2, "3-"); } - else { cprint(LINE_CPU+6, col2, "2-"); } - col2 +=2; + if (temp == 0x0) { rcd = 4; } + if (temp == 0x1) { rcd = 3; } + else { rcd = 2; } // RAS Precharge (tRP) temp = (drt&0x3); - if (temp == 0x0) { cprint(LINE_CPU+6, col2, "4-"); } - if (temp == 0x1) { cprint(LINE_CPU+6, col2, "3-"); } - else { cprint(LINE_CPU+6, col2, "2-"); } - col2 +=2; + if (temp == 0x0) { rp = 4; } + if (temp == 0x1) { rp = 3; } + else { rp = 2; } // RAS Active to precharge (tRAS) temp = ((drt >> 9)& 0x3); - if (temp == 0x0) { cprint(LINE_CPU+6, col2, "8"); col2 +=7; } - if (temp == 0x1) { cprint(LINE_CPU+6, col2, "7"); col2 +=6; } - if (temp == 0x2) { cprint(LINE_CPU+6, col2, "6"); col2 +=5; } - if (temp == 0x3) { cprint(LINE_CPU+6, col2, "5"); col2 +=5; } - col2 +=1; + if (temp == 0x0) { ras = 8; } + if (temp == 0x1) { ras = 7; } + if (temp == 0x2) { ras = 6; } + if (temp == 0x3) { ras = 5; } + + print_ram_line(cas, rcd, rp, ras, 1); } static void poll_timings_amd64(void) { ulong dramtlr, dramclr; - int temp; + int temp, chan; + float tcas; int trcd, trp, tras ; - cprint(LINE_CPU+6, col2 +1, "/ CAS : "); - col2 += 9; - pci_conf_read(0, 24, 2, 0x88, 4, &dramtlr); pci_conf_read(0, 24, 2, 0x90, 4, &dramclr); - - if (((cpu_id.ext >> 16) & 0xF) >= 4) { + + if (cpu_id.vers.bits.extendedModel >= 4) { /* NEW K8 0Fh Family 90 nm (DDR2) */ // CAS Latency (tCAS) - temp = (dramtlr & 0x7) + 1; - dprint(LINE_CPU+6, col2, temp , 1 ,0); - cprint(LINE_CPU+6, col2 +1, "-"); col2 +=2; + tcas = (dramtlr & 0x7) + 1; // RAS-To-CAS (tRCD) trcd = ((dramtlr >> 4) & 0x3) + 3; - dprint(LINE_CPU+6, col2, trcd , 1 ,0); - cprint(LINE_CPU+6, col2 +1, "-"); col2 +=2; // RAS Precharge (tRP) trp = ((dramtlr >> 8) & 0x3) + 3; - dprint(LINE_CPU+6, col2, trp , 1 ,0); - cprint(LINE_CPU+6, col2 +1, "-"); col2 +=2; // RAS Active to precharge (tRAS) tras = ((dramtlr >> 12) & 0xF) + 3; - if (tras < 10){ - dprint(LINE_CPU+6, col2, tras , 1 ,0); col2 += 1; - } else { - dprint(LINE_CPU+6, col2, tras , 2 ,0); col2 += 2; - } - cprint(LINE_CPU+6, col2+1, "/"); col2 +=2; // Print 64 or 128 bits mode - if ((dramclr >> 11)&1) { - cprint(LINE_CPU+6, col2, " DDR2 (128 bits)"); - col2 +=16; + chan = 2; } else { - cprint(LINE_CPU+6, col2, " DDR2 (64 bits)"); - col2 +=15; + chan = 1; } } else { @@ -3159,48 +3543,41 @@ static void poll_timings_amd64(void) { // CAS Latency (tCAS) temp = (dramtlr & 0x7); - if (temp == 0x1) { cprint(LINE_CPU+6, col2, "2-"); col2 +=2; } - if (temp == 0x2) { cprint(LINE_CPU+6, col2, "3-"); col2 +=2; } - if (temp == 0x5) { cprint(LINE_CPU+6, col2, "2.5-"); col2 +=4; } + if (temp == 0x1) { tcas = 2; } + if (temp == 0x2) { tcas = 3; } + if (temp == 0x5) { tcas = 2.5; } // RAS-To-CAS (tRCD) trcd = ((dramtlr >> 12) & 0x7); - dprint(LINE_CPU+6, col2, trcd , 1 ,0); - cprint(LINE_CPU+6, col2 +1, "-"); col2 +=2; // RAS Precharge (tRP) trp = ((dramtlr >> 24) & 0x7); - dprint(LINE_CPU+6, col2, trp , 1 ,0); - cprint(LINE_CPU+6, col2 +1, "-"); col2 +=2; // RAS Active to precharge (tRAS) tras = ((dramtlr >> 20) & 0xF); - if (tras < 10){ - dprint(LINE_CPU+6, col2, tras , 1 ,0); col2 += 1; - } else { - dprint(LINE_CPU+6, col2, tras , 2 ,0); col2 += 2; - } - cprint(LINE_CPU+6, col2+1, "/"); col2 +=2; // Print 64 or 128 bits mode - if (((dramclr >> 16)&1) == 1) { - cprint(LINE_CPU+6, col2, " DDR1 (128 bits)"); - col2 +=16; + chan = 2; } else { - cprint(LINE_CPU+6, col2, " DDR1 (64 bits)"); - col2 +=15; + chan = 1; } } + + print_ram_line(tcas, trcd, trp, tras, chan); + } static void poll_timings_k10(void) { - ulong dramtlr, dramclr, dramchr; + ulong dramtlr, dramclr, dramchr, dramchrb; ulong offset = 0; - int cas, rcd, rp, rc, ras; + int cas, rcd, rp, ras, chan; pci_conf_read(0, 24, 2, 0x94, 4, &dramchr); + pci_conf_read(0, 24, 2, 0x194, 4, &dramchrb); + + if(((dramchr>>14) & 0x1) || ((dramchr>>14) & 0x1)) { chan = 1; } else { chan = 2; } // If Channel A not enabled, switch to channel B if(((dramchr>>14) & 0x1)) @@ -3218,57 +3595,104 @@ static void poll_timings_k10(void) { cas = (dramtlr & 0xF) + 4; rcd = ((dramtlr >> 4) & 0x7) + 5; rp = ((dramtlr >> 7) & 0x7) + 5; - ras = ((dramtlr >> 12) & 0xF) + 15; - rc = ((dramtlr >> 16) & 0x1F) + 11; + ras = ((dramtlr >> 12) & 0xF) + 15; } else { // DDR2-800 or less cas = (dramtlr & 0xF) + 1; rcd = ((dramtlr >> 4) & 0x3) + 3; rp = ((dramtlr >> 8) & 0x3) + 3; ras = ((dramtlr >> 12) & 0xF) + 3; - rc = ((dramtlr >> 16) & 0x1F) + 11; } + + print_ram_line(cas, rcd, rp, ras, chan); +} - print_timings_info(cas, rcd, rp, ras); - - cprint(LINE_CPU+6, col2, "/"); col2++; +static void poll_timings_k12(void) { + + ulong dramt0, dramlow, dimma, dimmb; + int cas, rcd, rp, ras, chan = 0; - //Print DDR2 or DDR3 - if ((dramchr >> 8)&1) { - cprint(LINE_CPU+6, col2+1, "DDR3"); - } else { - cprint(LINE_CPU+6, col2+1, "DDR2"); + pci_conf_read(0, 24, 2, 0x94, 4, &dimma); + pci_conf_read(0, 24, 2, 0x194, 4, &dimmb); + + if(((dimma >> 14) & 0x1) == 0) + { + chan++; + pci_conf_read(0, 24, 2, 0x88, 4, &dramlow); + pci_conf_write(0, 24, 2, 0xF0, 4, 0x00000040); + pci_conf_read(0, 24, 2, 0xF4, 4, &dramt0); } - col2 += 5; - // Print 64 or 128 bits mode - if ((dramclr >> 4)&1) { - cprint(LINE_CPU+6, col2+1, "(128 bits)"); - } else { - cprint(LINE_CPU+6, col2+1, "(64 bits)"); - } + if(((dimmb >> 14) & 0x1) == 0) + { + chan++; + pci_conf_read(0, 24, 2, 0x188, 4, &dramlow); + pci_conf_write(0, 24, 2, 0x1F0, 4, 0x00000040); + pci_conf_read(0, 24, 2, 0x1F4, 4, &dramt0); + } + + cas = (dramlow & 0xF) + 4; + rcd = (dramt0 & 0xF) + 5; + rp = ((dramt0 >> 8) & 0xF) + 5; + ras = ((dramt0 >> 16) & 0x1F) + 15; + print_ram_line(cas, rcd, rp, ras, chan); } + static void poll_timings_k14(void) { ulong dramt0, dramlow; - int cas, rcd, rp, rc, ras; + int cas, rcd, rp, ras; - pci_conf_read(0, 24, 2, 0x88, 4, &dramlow); + pci_conf_read(0, 24, 2, 0x88, 4, &dramlow); pci_conf_write(0, 24, 2, 0xF0, 4, 0x00000040); - pci_conf_read(0, 24, 2, 0xF4, 4, &dramt0); + pci_conf_read(0, 24, 2, 0xF4, 4, &dramt0); cas = (dramlow & 0xF) + 4; rcd = (dramt0 & 0xF) + 5; rp = ((dramt0 >> 8) & 0xF) + 5; ras = ((dramt0 >> 16) & 0x1F) + 15; - rc = ((dramt0 >> 24) & 0x3F) + 16; + + print_ram_line(cas, rcd, rp, ras, 1); +} - print_timings_info(cas, rcd, rp, ras); +static void poll_timings_k15(void) { - cprint(LINE_CPU+6, col2, "/ DDR3 (64 bits)"); + ulong dramp1, dramp2, dimma, dimmb; + int cas, rcd, rp, ras, chan = 0; + + pci_conf_read(0, 24, 2, 0x94, 4, &dimma); + pci_conf_read(0, 24, 2, 0x194, 4, &dimmb); + if(((dimma>>14) & 0x1) || ((dimmb>>14) & 0x1)) { chan = 1; } else { chan = 2; } + + pci_conf_read(0, 24, 2, 0x200, 4, &dramp1); + pci_conf_read(0, 24, 2, 0x204, 4, &dramp2); + + cas = dramp1 & 0x1F; + rcd = (dramp1 >> 8) & 0x1F; + rp = (dramp1 >> 16) & 0x1F; + ras = (dramp1 >> 24) & 0x3F; + + print_ram_line(cas, rcd, rp, ras, chan); +} +static void poll_timings_k16(void) { + + ulong dramt0, dramt1; + int cas, rcd, rp, rc, ras; + + pci_conf_read(0, 24, 2, 0x200, 4, &dramt0); + pci_conf_read(0, 24, 2, 0x204, 4, &dramt1); + + cas = (dramt0 & 0x1F); + rcd = ((dramt0 >> 8) & 0x1F); + rp = ((dramt0 >> 16) & 0x1F); + ras = ((dramt0 >> 24) & 0x3F); + + rc = (dramt1 & 0x3F); + + print_ram_line(cas, rcd, rp, ras, 1); } static void poll_timings_EP80579(void) { @@ -3285,14 +3709,16 @@ static void poll_timings_EP80579(void) { rp = ((drt1 >> 6) & 0x7) + 3; ras = ((drt2 >> 28) & 0xF) + 8; - print_timings_info(cas, rcd, rp, ras); + print_ram_line(cas, rcd, rp, ras, 0); } static void poll_timings_nf2(void) { ulong dramtlr, dramtlr2, dramtlr3, temp; ulong dimm1p, dimm2p, dimm3p; - + float cas; + int rcd, rp, ras, chan; + pci_conf_read(0, 0, 1, 0x90, 4, &dramtlr); pci_conf_read(0, 0, 1, 0xA0, 4, &dramtlr2); pci_conf_read(0, 0, 1, 0x84, 4, &dramtlr3); @@ -3300,77 +3726,54 @@ static void poll_timings_nf2(void) { pci_conf_read(0, 0, 2, 0x44, 4, &dimm2p); pci_conf_read(0, 0, 2, 0x48, 4, &dimm3p); - cprint(LINE_CPU+6, col2 +1, "/ CAS : "); - col2 += 9; - // CAS Latency (tCAS) temp = ((dramtlr2 >> 4) & 0x7); - if (temp == 0x2) { cprint(LINE_CPU+6, col2, "2-"); col2 +=2; } - if (temp == 0x3) { cprint(LINE_CPU+6, col2, "3-"); col2 +=2; } - if (temp == 0x6) { cprint(LINE_CPU+6, col2, "2.5-"); col2 +=4; } - + if (temp == 0x2) { cas = 2; } + if (temp == 0x3) { cas = 3; } + if (temp == 0x6) { cas = 2.5; } + // RAS-To-CAS (tRCD) - temp = ((dramtlr >> 20) & 0xF); - dprint(LINE_CPU+6, col2, temp , 1 ,0); - cprint(LINE_CPU+6, col2 +1, "-"); col2 +=2; + rcd = ((dramtlr >> 20) & 0xF); // RAS Precharge (tRP) - temp = ((dramtlr >> 28) & 0xF); - dprint(LINE_CPU+6, col2, temp , 1 ,0); - cprint(LINE_CPU+6, col2 +1, "-"); col2 +=2; + rp = ((dramtlr >> 28) & 0xF); // RAS Active to precharge (tRAS) - temp = ((dramtlr >> 15) & 0xF); - if (temp < 10){ - dprint(LINE_CPU+6, col2, temp , 1 ,0); col2 += 1; - } else { - dprint(LINE_CPU+6, col2, temp , 2 ,0); col2 += 2; - } - cprint(LINE_CPU+6, col2+1, "/"); col2 +=2; + ras = ((dramtlr >> 15) & 0xF); // Print 64 or 128 bits mode // If DIMM1 & DIMM3 or DIMM1 & DIMM2 populated, than Dual Channel. if ((dimm3p&1) + (dimm2p&1) == 2 || (dimm3p&1) + (dimm1p&1) == 2 ) { - cprint(LINE_CPU+6, col2, " Dual Channel (128 bits)"); - col2 +=24; + chan = 2; } else { - cprint(LINE_CPU+6, col2, " Single Channel (64 bits)"); - col2 +=15; + chan = 1; } - + print_ram_line(cas, rcd, rp, ras, chan); } static void poll_timings_us15w(void) { // Thanks for CDH optis - ulong dtr, temp; - + ulong dtr; + float cas; + int rcd, rp; + /* Find dramratio */ /* D0 MsgRd, 01 Dunit, 01 DTR */ pci_conf_write(0, 0, 0, 0xD0, 4, 0xD0010100 ); pci_conf_read(0, 0, 0, 0xD4, 4, &dtr ); - // Now, detect timings - cprint(LINE_CPU+5, col2 +1, "/ CAS : "); - col2 += 9; - // CAS Latency (tCAS) - temp = ((dtr >> 4) & 0x3) + 3; - dprint(LINE_CPU+5, col2, temp, 1 ,0); - cprint(LINE_CPU+5, col2+1, "-"); - col2 += 2; + cas = ((dtr >> 4) & 0x3) + 3; // RAS-To-CAS (tRCD) - temp = ((dtr >> 2) & 0x3) + 3; - dprint(LINE_CPU+5, col2, temp, 1 ,0); - cprint(LINE_CPU+5, col2+1, "-"); - col2 += 2; + rcd = ((dtr >> 2) & 0x3) + 3; // RAS Precharge (tRP) - temp = ((dtr >> 0) & 0x3) + 3; - dprint(LINE_CPU+5, col2, temp, 1 ,0); - col2 += 1; + rp = ((dtr >> 0) & 0x3) + 3; + + print_ram_line(cas, rcd, rp, 9, 1); } @@ -3378,7 +3781,7 @@ static void poll_timings_nhm(void) { ulong mc_channel_bank_timing, mc_control, mc_channel_mrs_value; float cas; - int rcd, rp, ras; + int rcd, rp, ras, chan; int fvc_bn = 4; /* Find which channels are populated */ @@ -3403,200 +3806,233 @@ static void poll_timings_nhm(void) { ras = (mc_channel_bank_timing >> 4) & 0x1F; rp = mc_channel_bank_timing & 0xF; - print_timings_info(cas, rcd, rp, ras); - // Print 1, 2 or 3 Channels if (mc_control == 1 || mc_control == 2 || mc_control == 4 ) { - cprint(LINE_CPU+6, col2, "/ Single Channel"); - col2 += 16; + chan = 1; } else if (mc_control == 7) { - cprint(LINE_CPU+6, col2, "/ Triple Channel"); - col2 += 16; + chan = 3; } else { - cprint(LINE_CPU+6, col2, "/ Dual Channel"); - col2 += 14; + chan = 2; } - + print_ram_line(cas, rcd, rp, ras, chan); + } +static void poll_timings_ct(void) +{ + + unsigned long mcr,mdr; + float cas; + int rcd, rp, ras; + + /* Build the MCR Message*/ + mcr = (0x10 << 24); // 10h = Read - 11h = Write + mcr += (0x01 << 16); // DRAM Registers located on port 01h + mcr += (0x01 << 8); // DRP = 00h, DTR0 = 01h, DTR1 = 02h, DTR2 = 03h + mcr &= 0xFFFFFFF0; // bit 03:00 RSVD + + /* Send Message to GMCH */ + pci_conf_write(0, 0, 0, 0xD0, 4, mcr); + + /* Read Answer from Sideband bus */ + pci_conf_read(0, 0, 0, 0xD4, 4, &mdr); + + // CAS Latency (tCAS) + cas = ((mdr >> 12)& 0x7) + 5.0f; + + // RAS-To-CAS (tRCD) + rcd = ((mdr >> 8)& 0x7) + 5; + + // RAS Precharge (tRP) + rp = ((mdr >> 4)& 0x7) + 5; + + // RAS is in DTR1. Read Again. + mcr = 0x10010200; // Quick Mode ! Awesome ! + pci_conf_write(0, 0, 0, 0xD0, 4, mcr); + pci_conf_read(0, 0, 0, 0xD4, 4, &mdr); + + // RAS Active to precharge (tRAS) + ras = (mdr >> 20) & 0xF; + + // Print + print_ram_line(cas, rcd, rp, ras, 1); + +} /* ------------------ Let's continue ------------------ */ /* ---------------------------------------------------- */ -static struct pci_memory_controller controllers[] = { +struct pci_memory_controller controllers[] = { /* Default unknown chipset */ - { 0, 0, "", 0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing }, + { 0, 0, "","", 0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing }, /* AMD */ - { 0x1022, 0x7006, "AMD 751", 0, poll_fsb_nothing, poll_timings_nothing, setup_amd751, poll_amd751 }, - { 0x1022, 0x700c, "AMD 762", 0, poll_fsb_nothing, poll_timings_nothing, setup_amd76x, poll_amd76x }, - { 0x1022, 0x700e, "AMD 761", 0, poll_fsb_nothing, poll_timings_nothing, setup_amd76x, poll_amd76x }, + { 0x1022, 0x7006, "AMD 751","SDRAM PC-100", 0, poll_fsb_nothing, poll_timings_nothing, setup_amd751, poll_nothing }, + { 0x1022, 0x700c, "AMD 762","DDR-SDRAM", 0, poll_fsb_nothing, poll_timings_nothing, setup_amd76x, poll_nothing }, + { 0x1022, 0x700e, "AMD 761","DDR-SDRAM", 0, poll_fsb_nothing, poll_timings_nothing, setup_amd76x, poll_nothing }, /* SiS */ - { 0x1039, 0x0600, "SiS 600", 0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing }, - { 0x1039, 0x0620, "SiS 620", 0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing }, - { 0x1039, 0x5600, "SiS 5600", 0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing }, - { 0x1039, 0x0645, "SiS 645", 0, poll_fsb_p4, poll_timings_nothing, setup_nothing, poll_nothing }, - { 0x1039, 0x0646, "SiS 645DX", 0, poll_fsb_p4, poll_timings_nothing, setup_nothing, poll_nothing }, - { 0x1039, 0x0630, "SiS 630", 0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing }, - { 0x1039, 0x0650, "SiS 650", 0, poll_fsb_p4, poll_timings_nothing, setup_nothing, poll_nothing }, - { 0x1039, 0x0651, "SiS 651", 0, poll_fsb_p4, poll_timings_nothing, setup_nothing, poll_nothing }, - { 0x1039, 0x0730, "SiS 730", 0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing }, - { 0x1039, 0x0735, "SiS 735", 0, poll_fsb_amd32, poll_timings_nothing, setup_nothing, poll_nothing }, - { 0x1039, 0x0740, "SiS 740", 0, poll_fsb_amd32, poll_timings_nothing, setup_nothing, poll_nothing }, - { 0x1039, 0x0745, "SiS 745", 0, poll_fsb_amd32, poll_timings_nothing, setup_nothing, poll_nothing }, - { 0x1039, 0x0748, "SiS 748", 0, poll_fsb_amd32, poll_timings_nothing, setup_nothing, poll_nothing }, - { 0x1039, 0x0655, "SiS 655", 0, poll_fsb_p4, poll_timings_nothing, setup_nothing, poll_nothing }, - { 0x1039, 0x0656, "SiS 656", 0, poll_fsb_p4, poll_timings_nothing, setup_nothing, poll_nothing }, - { 0x1039, 0x0648, "SiS 648", 0, poll_fsb_p4, poll_timings_nothing, setup_nothing, poll_nothing }, - { 0x1039, 0x0649, "SiS 649", 0, poll_fsb_p4, poll_timings_nothing, setup_nothing, poll_nothing }, - { 0x1039, 0x0661, "SiS 661", 0, poll_fsb_p4, poll_timings_nothing, setup_nothing, poll_nothing }, - { 0x1039, 0x0671, "SiS 671", 0, poll_fsb_p4, poll_timings_nothing, setup_nothing, poll_nothing }, - { 0x1039, 0x0672, "SiS 672", 0, poll_fsb_p4, poll_timings_nothing, setup_nothing, poll_nothing }, + { 0x1039, 0x0600, "SiS 600","EDO/SDRAM", 0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing }, + { 0x1039, 0x0620, "SiS 620","SDRAM", 0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing }, + { 0x1039, 0x5600, "SiS 5600","SDRAM", 0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing }, + { 0x1039, 0x0645, "SiS 645","DDR-SDRAM", 0, poll_fsb_p4, poll_timings_nothing, setup_nothing, poll_nothing }, + { 0x1039, 0x0646, "SiS 645DX","DDR-SDRAM", 0, poll_fsb_p4, poll_timings_nothing, setup_nothing, poll_nothing }, + { 0x1039, 0x0630, "SiS 630","SDRAM", 0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing }, + { 0x1039, 0x0650, "SiS 650","DDR-SDRAM", 0, poll_fsb_p4, poll_timings_nothing, setup_nothing, poll_nothing }, + { 0x1039, 0x0651, "SiS 651","DDR-SDRAM", 0, poll_fsb_p4, poll_timings_nothing, setup_nothing, poll_nothing }, + { 0x1039, 0x0730, "SiS 730","SDRAM", 0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing }, + { 0x1039, 0x0735, "SiS 735","DDR-SDRAM", 0, poll_fsb_amd32, poll_timings_nothing, setup_nothing, poll_nothing }, + { 0x1039, 0x0740, "SiS 740","DDR-SDRAM", 0, poll_fsb_amd32, poll_timings_nothing, setup_nothing, poll_nothing }, + { 0x1039, 0x0745, "SiS 745","DDR-SDRAM", 0, poll_fsb_amd32, poll_timings_nothing, setup_nothing, poll_nothing }, + { 0x1039, 0x0748, "SiS 748","DDR-SDRAM", 0, poll_fsb_amd32, poll_timings_nothing, setup_nothing, poll_nothing }, + { 0x1039, 0x0655, "SiS 655","DDR-SDRAM", 0, poll_fsb_p4, poll_timings_nothing, setup_nothing, poll_nothing }, + { 0x1039, 0x0656, "SiS 656","DDR/DDR2-SDRAM", 0, poll_fsb_p4, poll_timings_nothing, setup_nothing, poll_nothing }, + { 0x1039, 0x0648, "SiS 648","DDR-SDRAM", 0, poll_fsb_p4, poll_timings_nothing, setup_nothing, poll_nothing }, + { 0x1039, 0x0649, "SiS 649","DDR-SDRAM", 0, poll_fsb_p4, poll_timings_nothing, setup_nothing, poll_nothing }, + { 0x1039, 0x0661, "SiS 661","DDR-SDRAM", 0, poll_fsb_p4, poll_timings_nothing, setup_nothing, poll_nothing }, + { 0x1039, 0x0671, "SiS 671","DDR2-SDRAM", 0, poll_fsb_p4, poll_timings_nothing, setup_nothing, poll_nothing }, + { 0x1039, 0x0672, "SiS 672","DDR2-SDRAM", 0, poll_fsb_p4, poll_timings_nothing, setup_nothing, poll_nothing }, /* ALi */ - { 0x10b9, 0x1531, "ALi Aladdin 4", 0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing }, - { 0x10b9, 0x1541, "ALi Aladdin 5", 0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing }, - { 0x10b9, 0x1644, "ALi Aladdin M1644", 0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing }, + { 0x10b9, 0x1531, "ALi Aladdin 4","EDO/SDRAM", 0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing }, + { 0x10b9, 0x1541, "ALi Aladdin 5","EDO/SDRAM", 0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing }, + { 0x10b9, 0x1644, "ALi Aladdin M1644","SDRAM", 0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing }, /* ATi */ - { 0x1002, 0x5830, "ATi Radeon 9100 IGP", 0, poll_fsb_p4, poll_timings_nothing, setup_nothing, poll_nothing }, - { 0x1002, 0x5831, "ATi Radeon 9100 IGP", 0, poll_fsb_p4, poll_timings_nothing, setup_nothing, poll_nothing }, - { 0x1002, 0x5832, "ATi Radeon 9100 IGP", 0, poll_fsb_p4, poll_timings_nothing, setup_nothing, poll_nothing }, - { 0x1002, 0x5833, "ATi Radeon 9100 IGP", 0, poll_fsb_p4, poll_timings_nothing, setup_nothing, poll_nothing }, - { 0x1002, 0x5954, "ATi Radeon Xpress 200", 0, poll_fsb_p4, poll_timings_nothing, setup_nothing, poll_nothing }, - { 0x1002, 0x5A41, "ATi Radeon Xpress 200", 0, poll_fsb_p4, poll_timings_nothing, setup_nothing, poll_nothing }, + { 0x1002, 0x5830, "ATi Radeon 9100 IGP","DDR-SDRAM", 0, poll_fsb_p4, poll_timings_nothing, setup_nothing, poll_nothing }, + { 0x1002, 0x5831, "ATi Radeon 9100 IGP","DDR-SDRAM", 0, poll_fsb_p4, poll_timings_nothing, setup_nothing, poll_nothing }, + { 0x1002, 0x5832, "ATi Radeon 9100 IGP","DDR-SDRAM", 0, poll_fsb_p4, poll_timings_nothing, setup_nothing, poll_nothing }, + { 0x1002, 0x5833, "ATi Radeon 9100 IGP","DDR-SDRAM", 0, poll_fsb_p4, poll_timings_nothing, setup_nothing, poll_nothing }, + { 0x1002, 0x5954, "ATi Xpress 200","DDR-SDRAM", 0, poll_fsb_p4, poll_timings_nothing, setup_nothing, poll_nothing }, + { 0x1002, 0x5A41, "ATi Xpress 200","DDR-SDRAM", 0, poll_fsb_p4, poll_timings_nothing, setup_nothing, poll_nothing }, /* nVidia */ - { 0x10de, 0x01A4, "nVidia nForce", 0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing }, - { 0x10de, 0x01E0, "nVidia nForce2 SPP", 0, poll_fsb_nf2, poll_timings_nf2, setup_nothing, poll_nothing }, - { 0x10de, 0x0071, "nForce4 SLI Intel Edition", 0, poll_fsb_nf4ie, poll_timings_nf4ie, setup_nothing, poll_nothing }, + { 0x10de, 0x01A4, "nVidia nForce","DDR-SDRAM", 0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing }, + { 0x10de, 0x01E0, "nVidia nForce2 SPP","", 0, poll_fsb_nf2, poll_timings_nf2, setup_nothing, poll_nothing }, + { 0x10de, 0x0071, "nForce4 SLI","", 0, poll_fsb_nf4ie, poll_timings_nf4ie, setup_nothing, poll_nothing }, /* VIA */ - { 0x1106, 0x0305, "VIA KT133/KT133A", 0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing }, - { 0x1106, 0x0391, "VIA KX133", 0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing }, - { 0x1106, 0x0501, "VIA MVP4", 0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing }, - { 0x1106, 0x0585, "VIA VP/VPX", 0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing }, - { 0x1106, 0x0595, "VIA VP2", 0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing }, - { 0x1106, 0x0597, "VIA VP3", 0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing }, - { 0x1106, 0x0598, "VIA MVP3", 0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing }, - { 0x1106, 0x0691, "VIA Apollo Pro/133/133A", 0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing }, - { 0x1106, 0x0693, "VIA Apollo Pro+", 0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing }, - { 0x1106, 0x0601, "VIA PLE133", 0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing }, - { 0x1106, 0x3099, "VIA KT266(A)/KT333", 0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing }, - { 0x1106, 0x3189, "VIA KT400(A)/600", 0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing }, - { 0x1106, 0x0269, "VIA KT880", 0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing }, - { 0x1106, 0x3205, "VIA KM400", 0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing }, - { 0x1106, 0x3116, "VIA KM266", 0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing }, - { 0x1106, 0x3156, "VIA KN266", 0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing }, - { 0x1106, 0x3123, "VIA CLE266", 0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing }, - { 0x1106, 0x0198, "VIA PT800", 0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing }, - { 0x1106, 0x3258, "VIA PT880", 0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing }, + { 0x1106, 0x0305, "VIA KT133/KT133A","SDRAM", 0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing }, + { 0x1106, 0x0391, "VIA KX133","SDRAM", 0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing }, + { 0x1106, 0x0501, "VIA MVP4","EDO/SDRAM", 0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing }, + { 0x1106, 0x0585, "VIA VP/VPX","EDO/SDRAM", 0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing }, + { 0x1106, 0x0595, "VIA VP2","EDO/SDRAM", 0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing }, + { 0x1106, 0x0597, "VIA VP3","EDO/SDRAM", 0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing }, + { 0x1106, 0x0598, "VIA MVP3","EDO/SDRAM", 0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing }, + { 0x1106, 0x0691, "VIA Apollo Pro 133(A)","SDRAM", 0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing }, + { 0x1106, 0x0693, "VIA Apollo Pro+","SDRAM", 0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing }, + { 0x1106, 0x0601, "VIA PLE133","SDRAM", 0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing }, + { 0x1106, 0x3099, "VIA KT266(A)/KT333","DDR-SDRAM", 0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing }, + { 0x1106, 0x3189, "VIA KT400(A)/600","DDR-SDRAM", 0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing }, + { 0x1106, 0x0269, "VIA KT880","DDR-SDRAM", 0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing }, + { 0x1106, 0x3205, "VIA KM400","DDR-SDRAM", 0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing }, + { 0x1106, 0x3116, "VIA KM266","DDR-SDRAM", 0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing }, + { 0x1106, 0x3156, "VIA KN266","DDR-SDRAM", 0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing }, + { 0x1106, 0x3123, "VIA CLE266","DDR-SDRAM", 0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing }, + { 0x1106, 0x0198, "VIA PT800","DDR-SDRAM", 0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing }, + { 0x1106, 0x3258, "VIA PT880","DDR2-SDRAM", 0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing }, /* Serverworks */ - { 0x1166, 0x0008, "CNB20HE", 0, poll_fsb_nothing, poll_timings_nothing, setup_cnb20, poll_nothing }, - { 0x1166, 0x0009, "CNB20LE", 0, poll_fsb_nothing, poll_timings_nothing, setup_cnb20, poll_nothing }, + { 0x1166, 0x0008, "CNB20HE","SDRAM", 0, poll_fsb_nothing, poll_timings_nothing, setup_cnb20, poll_nothing }, + { 0x1166, 0x0009, "CNB20LE","SDRAM", 0, poll_fsb_nothing, poll_timings_nothing, setup_cnb20, poll_nothing }, /* Intel */ - { 0x8086, 0x1130, "Intel i815", 0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing }, - { 0x8086, 0x122d, "Intel i430FX", 0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing }, - { 0x8086, 0x1235, "Intel i430MX", 0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing }, - { 0x8086, 0x1237, "Intel i440FX", 0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing }, - { 0x8086, 0x1250, "Intel i430HX", 0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing }, - { 0x8086, 0x1A21, "Intel i840", 0, poll_fsb_nothing, poll_timings_nothing, setup_i840, poll_i840 }, - { 0x8086, 0x1A30, "Intel i845", 0, poll_fsb_p4, poll_timings_nothing, setup_i845, poll_i845 }, - { 0x8086, 0x2560, "Intel i845E/G/PE/GE",0, poll_fsb_p4, poll_timings_nothing, setup_i845, poll_i845 }, - { 0x8086, 0x2500, "Intel i820", 0, poll_fsb_nothing, poll_timings_nothing, setup_i820, poll_i820 }, - { 0x8086, 0x2530, "Intel i850", 0, poll_fsb_p4, poll_timings_nothing, setup_i850, poll_i850 }, - { 0x8086, 0x2531, "Intel i860", 1, poll_fsb_nothing, poll_timings_nothing, setup_i860, poll_i860 }, - { 0x8086, 0x7030, "Intel i430VX", 0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing }, - { 0x8086, 0x7100, "Intel i430TX", 0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing }, - { 0x8086, 0x7120, "Intel i810", 0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing }, - { 0x8086, 0x7122, "Intel i810", 0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing }, - { 0x8086, 0x7124, "Intel i810E", 0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing }, - { 0x8086, 0x7180, "Intel i440[LE]X", 0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing }, - { 0x8086, 0x7190, "Intel i440BX", 0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing }, - { 0x8086, 0x7192, "Intel i440BX", 0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing }, - { 0x8086, 0x71A0, "Intel i440GX", 0, poll_fsb_nothing, poll_timings_nothing, setup_i440gx, poll_i440gx }, - { 0x8086, 0x71A2, "Intel i440GX", 0, poll_fsb_nothing, poll_timings_nothing, setup_i440gx, poll_i440gx }, - { 0x8086, 0x84C5, "Intel i450GX", 0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing }, - { 0x8086, 0x2540, "Intel E7500", 1, poll_fsb_p4, poll_timings_E750x, setup_iE7xxx, poll_iE7xxx }, - { 0x8086, 0x254C, "Intel E7501", 1, poll_fsb_p4, poll_timings_E750x, setup_iE7xxx, poll_iE7xxx }, - { 0x8086, 0x255d, "Intel E7205", 0, poll_fsb_p4, poll_timings_nothing, setup_iE7xxx, poll_iE7xxx }, - { 0x8086, 0x3592, "Intel E7320", 0, poll_fsb_p4, poll_timings_E7520, setup_iE7520, poll_iE7520 }, - { 0x8086, 0x2588, "Intel E7221", 1, poll_fsb_i925, poll_timings_i925, setup_i925, poll_iE7221 }, - { 0x8086, 0x3590, "Intel E7520", 0, poll_fsb_p4, poll_timings_E7520, setup_iE7520, poll_nothing }, - { 0x8086, 0x2600, "Intel E8500", 0, poll_fsb_p4, poll_timings_nothing, setup_nothing, poll_nothing }, - { 0x8086, 0x2570, "Intel i848/i865", 0, poll_fsb_i875, poll_timings_i875, setup_i875, poll_nothing }, - { 0x8086, 0x2578, "Intel i875P", 0, poll_fsb_i875, poll_timings_i875, setup_i875, poll_i875 }, - { 0x8086, 0x2550, "Intel E7505", 0, poll_fsb_p4, poll_timings_nothing, setup_iE7xxx, poll_iE7xxx }, - { 0x8086, 0x3580, "Intel ", 0, poll_fsb_i855, poll_timings_i852, setup_nothing, poll_nothing }, - { 0x8086, 0x3340, "Intel i855PM", 0, poll_fsb_i855, poll_timings_i855, setup_nothing, poll_nothing }, - { 0x8086, 0x2580, "Intel i915P/G", 0, poll_fsb_i925, poll_timings_i925, setup_i925, poll_nothing }, - { 0x8086, 0x2590, "Intel i915PM/GM", 0, poll_fsb_i925, poll_timings_i925, setup_i925, poll_nothing }, - { 0x8086, 0x2584, "Intel i925X/XE", 0, poll_fsb_i925, poll_timings_i925, setup_i925, poll_iE7221 }, - { 0x8086, 0x2770, "Intel i945P/G", 0, poll_fsb_i945, poll_timings_i925, setup_i925, poll_nothing }, - { 0x8086, 0x27A0, "Intel i945GM/PM", 0, poll_fsb_i945, poll_timings_i925, setup_i925, poll_nothing }, - { 0x8086, 0x27AC, "Intel i945GME", 0, poll_fsb_i945, poll_timings_i925, setup_i925, poll_nothing }, - { 0x8086, 0x2774, "Intel i955X", 0, poll_fsb_i945, poll_timings_i925, setup_i925, poll_nothing}, - { 0x8086, 0x277C, "Intel i975X", 0, poll_fsb_i975, poll_timings_i925, setup_i925, poll_nothing}, - { 0x8086, 0x2970, "Intel i946PL/GZ", 0, poll_fsb_i965, poll_timings_i965, setup_p35, poll_nothing}, - { 0x8086, 0x2990, "Intel Q963/Q965", 0, poll_fsb_i965, poll_timings_i965, setup_p35, poll_nothing}, - { 0x8086, 0x29A0, "Intel P965/G965", 0, poll_fsb_i965, poll_timings_i965, setup_p35, poll_nothing}, - { 0x8086, 0x2A00, "Intel GM965/GL960", 0, poll_fsb_im965, poll_timings_im965, setup_p35, poll_nothing}, - { 0x8086, 0x2A10, "Intel GME965/GLE960",0, poll_fsb_im965, poll_timings_im965, setup_p35, poll_nothing}, - { 0x8086, 0x2A40, "Intel PM/GM45/47", 0, poll_fsb_im965, poll_timings_im965, setup_p35, poll_nothing}, - { 0x8086, 0x29B0, "Intel Q35", 0, poll_fsb_i965, poll_timings_p35, setup_p35, poll_nothing}, - { 0x8086, 0x29C0, "Intel P35/G33", 0, poll_fsb_i965, poll_timings_p35, setup_p35, poll_nothing}, - { 0x8086, 0x29D0, "Intel Q33", 0, poll_fsb_i965, poll_timings_p35, setup_p35, poll_nothing}, - { 0x8086, 0x29E0, "Intel X38/X48", 0, poll_fsb_i965, poll_timings_p35, setup_p35, poll_nothing}, - { 0x8086, 0x29F0, "Intel 3200/3210", 0, poll_fsb_i965, poll_timings_p35, setup_p35, poll_nothing}, - { 0x8086, 0x2E10, "Intel Q45/Q43", 0, poll_fsb_i965, poll_timings_p35, setup_p35, poll_nothing}, - { 0x8086, 0x2E20, "Intel P45/G45", 0, poll_fsb_i965, poll_timings_p35, setup_p35, poll_nothing}, - { 0x8086, 0x2E30, "Intel G41", 0, poll_fsb_i965, poll_timings_p35, setup_p35, poll_nothing}, - { 0x8086, 0x4001, "Intel 5400A", 0, poll_fsb_5400, poll_timings_5400, setup_E5400, poll_nothing}, - { 0x8086, 0x4003, "Intel 5400B", 0, poll_fsb_5400, poll_timings_5400, setup_E5400, poll_nothing}, - { 0x8086, 0x25D8, "Intel 5000P", 0, poll_fsb_5400, poll_timings_5400, setup_E5400, poll_nothing}, - { 0x8086, 0x25D4, "Intel 5000V", 0, poll_fsb_5400, poll_timings_5400, setup_E5400, poll_nothing}, - { 0x8086, 0x25C0, "Intel 5000X", 0, poll_fsb_5400, poll_timings_5400, setup_E5400, poll_nothing}, - { 0x8086, 0x25D0, "Intel 5000Z", 0, poll_fsb_5400, poll_timings_5400, setup_E5400, poll_nothing}, - { 0x8086, 0x5020, "Intel EP80579", 0, poll_fsb_p4, poll_timings_EP80579, setup_nothing, poll_nothing }, - { 0x8086, 0x8100, "Intel US15W", 0, poll_fsb_us15w, poll_timings_us15w, setup_nothing, poll_nothing}, - { 0x8086, 0x8101, "Intel UL11L/US15L", 0, poll_fsb_us15w, poll_timings_us15w, setup_nothing, poll_nothing}, - - /* Integrated Memory Controllers */ - { 0xFFFF, 0x0001, "Core IMC", 0, poll_fsb_nhm, poll_timings_nhm, setup_nhm, poll_nothing}, - { 0xFFFF, 0x0002, "Core IMC 32nm", 0, poll_fsb_nhm32, poll_timings_nhm, setup_nhm32, poll_nothing}, - { 0xFFFF, 0x0003, "Core IMC 32nm", 0, poll_fsb_wmr, poll_timings_wmr, setup_wmr, poll_nothing}, - { 0xFFFF, 0x0004, "SNB IMC 32nm", 0, poll_fsb_snb, poll_timings_snb, setup_wmr, poll_nothing}, - { 0xFFFF, 0x0100, "AMD K8 IMC", 0, poll_fsb_amd64, poll_timings_amd64, setup_amd64, poll_amd64 }, - { 0xFFFF, 0x0101, "AMD K10 IMC", 0, poll_fsb_k10, poll_timings_k10, setup_k10, poll_nothing }, - { 0xFFFF, 0x0102, "AMD APU IMC", 0, poll_fsb_k14, poll_timings_k14, setup_nothing, poll_nothing }, - - /* Fail Safe */ - { 0xFFFF, 0xFFFF, "", 0, poll_fsb_failsafe, poll_timings_nothing, setup_nothing, poll_nothing } + { 0x8086, 0x1130, "Intel i815","SDRAM", 0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing }, + { 0x8086, 0x122d, "Intel i430FX","EDO DRAM",0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing }, + { 0x8086, 0x1235, "Intel i430MX","EDO DRAM",0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing }, + { 0x8086, 0x1237, "Intel i440FX","EDO DRAM",0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing }, + { 0x8086, 0x1250, "Intel i430HX","EDO DRAM",0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing }, + { 0x8086, 0x1A21, "Intel i840","RDRAM", 0, poll_fsb_nothing, poll_timings_nothing, setup_i840, poll_nothing }, + { 0x8086, 0x1A30, "Intel i845","SDR/DDR", 0, poll_fsb_p4, poll_timings_nothing, setup_i845, poll_nothing }, + { 0x8086, 0x2560, "Intel i845E/G/PE/GE","", 0, poll_fsb_p4, poll_timings_nothing, setup_i845, poll_nothing }, + { 0x8086, 0x2500, "Intel i820","RDRAM", 0, poll_fsb_nothing, poll_timings_nothing, setup_i820, poll_nothing }, + { 0x8086, 0x2530, "Intel i850","RDRAM", 0, poll_fsb_p4, poll_timings_nothing, setup_i850, poll_nothing }, + { 0x8086, 0x2531, "Intel i860","RDRAM", 0, poll_fsb_nothing, poll_timings_nothing, setup_i860, poll_nothing }, + { 0x8086, 0x7030, "Intel i430VX","SDRAM", 0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing }, + { 0x8086, 0x7100, "Intel i430TX","SDRAM", 0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing }, + { 0x8086, 0x7120, "Intel i810","SDRAM", 0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing }, + { 0x8086, 0x7122, "Intel i810","SDRAM", 0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing }, + { 0x8086, 0x7124, "Intel i810E","SDRAM", 0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing }, + { 0x8086, 0x7180, "Intel i440[LE]X","SDRAM",0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing }, + { 0x8086, 0x7190, "Intel i440BX","SDRAM", 0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing }, + { 0x8086, 0x7192, "Intel i440BX","SDRAM", 0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing }, + { 0x8086, 0x71A0, "Intel i440GX","SDRAM", 0, poll_fsb_nothing, poll_timings_nothing, setup_i440gx, poll_nothing }, + { 0x8086, 0x71A2, "Intel i440GX","SDRAM", 0, poll_fsb_nothing, poll_timings_nothing, setup_i440gx, poll_nothing }, + { 0x8086, 0x84C5, "Intel i450GX","SDRAM", 0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing }, + { 0x8086, 0x2540, "Intel E7500","DDR-SDRAM",0, poll_fsb_p4, poll_timings_E750x, setup_iE7xxx, poll_nothing }, + { 0x8086, 0x254C, "Intel E7501","DDR-SDRAM",0, poll_fsb_p4, poll_timings_E750x, setup_iE7xxx, poll_nothing }, + { 0x8086, 0x255d, "Intel E7205","DDR-SDRAM",0, poll_fsb_p4, poll_timings_nothing, setup_iE7xxx, poll_nothing }, + { 0x8086, 0x3592, "Intel E7320","DDR-SDRAM",0, poll_fsb_p4, poll_timings_E7520, setup_iE7520, poll_nothing }, + { 0x8086, 0x2588, "Intel E7221","DDR-SDRAM",0, poll_fsb_i925, poll_timings_i925, setup_i925, poll_nothing }, + { 0x8086, 0x3590, "Intel E7520","DDR-SDRAM",0, poll_fsb_p4, poll_timings_E7520, setup_iE7520, poll_nothing }, + { 0x8086, 0x2600, "Intel E8500","DDR-SDRAM",0, poll_fsb_p4, poll_timings_nothing, setup_nothing, poll_nothing }, + { 0x8086, 0x2570, "Intel i848/i865","", 0, poll_fsb_i875, poll_timings_i875, setup_i875, poll_nothing }, + { 0x8086, 0x2578, "Intel i875P","", 0, poll_fsb_i875, poll_timings_i875, setup_i875, poll_nothing }, + { 0x8086, 0x2550, "Intel E7505","DDR-SDRAM",0, poll_fsb_p4, poll_timings_nothing, setup_iE7xxx, poll_nothing }, + { 0x8086, 0x3580, "Intel i852P/i855G","", 0, poll_fsb_i855, poll_timings_i852, setup_nothing, poll_nothing }, + { 0x8086, 0x3340, "Intel i855PM","", 0, poll_fsb_i855, poll_timings_i855, setup_nothing, poll_nothing }, + { 0x8086, 0x2580, "Intel i915P/G","", 0, poll_fsb_i925, poll_timings_i925, setup_i925, poll_nothing }, + { 0x8086, 0x2590, "Intel i915PM/GM","", 0, poll_fsb_i925, poll_timings_i925, setup_i925, poll_nothing }, + { 0x8086, 0x2584, "Intel i925X/XE","", 0, poll_fsb_i925, poll_timings_i925, setup_i925, poll_nothing }, + { 0x8086, 0x2770, "Intel i945P/G","", 0, poll_fsb_i945, poll_timings_i925, setup_i925, poll_nothing }, + { 0x8086, 0x27A0, "Intel i945GM/PM","", 0, poll_fsb_i945, poll_timings_i925, setup_i925, poll_nothing }, + { 0x8086, 0x27AC, "Intel i945GME","", 0, poll_fsb_i945gme, poll_timings_i925, setup_i925, poll_nothing }, + { 0x8086, 0x2774, "Intel i955X","", 0, poll_fsb_i945, poll_timings_i925, setup_i925, poll_nothing}, + { 0x8086, 0x277C, "Intel i975X","", 0, poll_fsb_i975, poll_timings_i925, setup_i925, poll_nothing}, + { 0x8086, 0x2970, "Intel i946PL/GZ","", 0, poll_fsb_i965, poll_timings_i965, setup_p35, poll_nothing}, + { 0x8086, 0x2990, "Intel Q963/Q965","", 0, poll_fsb_i965, poll_timings_i965, setup_p35, poll_nothing}, + { 0x8086, 0x29A0, "Intel P965/G965","", 0, poll_fsb_i965, poll_timings_i965, setup_p35, poll_nothing}, + { 0x8086, 0x2A00, "Intel GM965/GL960","", 0, poll_fsb_im965, poll_timings_im965, setup_p35, poll_nothing}, + { 0x8086, 0x2A10, "Intel GME965/GLE960","", 0, poll_fsb_im965, poll_timings_im965, setup_p35, poll_nothing}, + { 0x8086, 0x2A40, "Intel PM/GM45/47","", 0, poll_fsb_im965, poll_timings_im965, setup_p35, poll_nothing}, + { 0x8086, 0x29B0, "Intel Q35","", 0, poll_fsb_p35, poll_timings_p35, setup_p35, poll_nothing}, + { 0x8086, 0x29C0, "Intel P35/G33","", 0, poll_fsb_p35, poll_timings_p35, setup_p35, poll_nothing}, + { 0x8086, 0x29D0, "Intel Q33","", 0, poll_fsb_p35, poll_timings_p35, setup_p35, poll_nothing}, + { 0x8086, 0x29E0, "Intel X38/X48","", 0, poll_fsb_p35, poll_timings_p35, setup_p35, poll_nothing}, + { 0x8086, 0x29F0, "Intel 3200/3210","", 0, poll_fsb_p35, poll_timings_p35, setup_p35, poll_nothing}, + { 0x8086, 0x2E10, "Intel Q45/Q43","", 0, poll_fsb_p35, poll_timings_p35, setup_p35, poll_nothing}, + { 0x8086, 0x2E20, "Intel P45/G45","", 0, poll_fsb_p35, poll_timings_p35, setup_p35, poll_nothing}, + { 0x8086, 0x2E30, "Intel G41","", 0, poll_fsb_p35, poll_timings_p35, setup_p35, poll_nothing}, + { 0x8086, 0x4001, "Intel 5400A","", 0, poll_fsb_5400, poll_timings_5400, setup_E5400, poll_nothing}, + { 0x8086, 0x4003, "Intel 5400B","", 0, poll_fsb_5400, poll_timings_5400, setup_E5400, poll_nothing}, + { 0x8086, 0x25D8, "Intel 5000P","", 0, poll_fsb_5400, poll_timings_5400, setup_E5400, poll_nothing}, + { 0x8086, 0x25D4, "Intel 5000V","", 0, poll_fsb_5400, poll_timings_5400, setup_E5400, poll_nothing}, + { 0x8086, 0x25C0, "Intel 5000X","", 0, poll_fsb_5400, poll_timings_5400, setup_E5400, poll_nothing}, + { 0x8086, 0x25D0, "Intel 5000Z","", 0, poll_fsb_5400, poll_timings_5400, setup_E5400, poll_nothing}, + { 0x8086, 0x5020, "Intel EP80579","", 0, poll_fsb_p4, poll_timings_EP80579, setup_nothing, poll_nothing }, + { 0x8086, 0x8100, "Intel US15W","", 0, poll_fsb_us15w, poll_timings_us15w, setup_nothing, poll_nothing}, + { 0x8086, 0x8101, "Intel UL11L/US15L","", 0, poll_fsb_us15w, poll_timings_us15w, setup_nothing, poll_nothing}, + + /* INTEL IMC (Integrated Memory Controllers) */ + { 0xFFFF, 0x0001, "Core IMC","", 0, poll_fsb_nhm, poll_timings_nhm, setup_nhm, poll_nothing}, + { 0xFFFF, 0x0002, "Core IMC","", 0, poll_fsb_nhm32, poll_timings_nhm, setup_nhm32, poll_nothing}, + { 0xFFFF, 0x0003, "Core IMC","", 0, poll_fsb_wmr, poll_timings_wmr, setup_wmr, poll_nothing}, + { 0xFFFF, 0x0004, "SNB IMC","", 0, poll_fsb_snb, poll_timings_snb, setup_wmr, poll_nothing}, + { 0xFFFF, 0x0005, "SNB-E IMC","", 0, poll_fsb_snbe, poll_timings_snbe, setup_wmr, poll_nothing}, + { 0xFFFF, 0x0006, "IVB IMC","", 0, poll_fsb_ivb, poll_timings_snb, setup_wmr, poll_nothing}, + { 0xFFFF, 0x0007, "HSW IMC","", 0, poll_fsb_ivb, poll_timings_hsw, setup_wmr, poll_nothing}, + { 0xFFFF, 0x0008, "PineView IMC","", 0, poll_fsb_p35, poll_timings_p35, setup_p35, poll_nothing}, + { 0xFFFF, 0x0009, "CedarTrail IMC","", 0, poll_fsb_ct, poll_timings_ct, setup_nothing, poll_nothing}, + + /* AMD IMC (Integrated Memory Controllers) */ + { 0xFFFF, 0x0100, "AMD K8 IMC","", 0, poll_fsb_amd64, poll_timings_amd64, setup_amd64, poll_nothing }, + { 0xFFFF, 0x0101, "AMD K10 IMC","", 0, poll_fsb_k10, poll_timings_k10, setup_k10, poll_nothing }, + { 0xFFFF, 0x0102, "AMD K12 IMC","", 0, poll_fsb_k12, poll_timings_k12, setup_apu, poll_nothing }, + { 0xFFFF, 0x0103, "AMD K14 IMC","", 0, poll_fsb_k14, poll_timings_k14, setup_apu, poll_nothing }, + { 0xFFFF, 0x0104, "AMD K15 IMC","", 0, poll_fsb_k15, poll_timings_k15, setup_apu, poll_nothing }, + { 0xFFFF, 0x0105, "AMD K16 IMC","", 0, poll_fsb_k16, poll_timings_k16, setup_apu, poll_nothing } }; static void print_memory_controller(void) { - /* Print memory controller info */ - - int d; - char *name; + /* Print memory controller info */ if (ctrl.index == 0) { return; } - /* Print the controller name */ - name = controllers[ctrl.index].name; - col = 10; - cprint(LINE_CPU+5, col, name); - /* Now figure out how much I just printed */ - while(name[col - 10] != '\0') { - col++; - } /* Now print the memory controller capabilities */ + /* cprint(LINE_CPU+5, col, " "); col++; if (ctrl.cap == ECC_UNKNOWN) { return; @@ -3642,15 +4078,16 @@ static void print_memory_controller(void) cprint(LINE_CPU+5, col +7, on?"+ ":"- "); col += 9; } - + */ + + + /* Print advanced caracteristics */ col2 = 0; - d = get_key(); - /* if F1 is pressed, disable advanced detection */ - if (d != 0x3B) { + controllers[ctrl.index].poll_fsb(); controllers[ctrl.index].poll_timings(); - } + } @@ -3658,7 +4095,6 @@ void find_controller(void) { unsigned long vendor; unsigned long device; - extern struct cpu_ident cpu_id; int i; int result; result = pci_conf_read(ctrl.bus, ctrl.dev, ctrl.fn, PCI_VENDOR_ID, 2, &vendor); @@ -3666,10 +4102,12 @@ void find_controller(void) // Detect IMC by CPUID if(imc_type) { vendor = 0xFFFF; device = imc_type; } - if(fail_safe) { vendor = 0xFFFF; device = 0xFFFF; } - + if(v->fail_safe & 1) { vendor = 0xFFFF; device = 0xFFFF; } + + //hprint(11,0,vendor); hprint(11,10,device); + ctrl.index = 0; - if (result == 0) { + if (result == 0 || imc_type) { for(i = 1; i < sizeof(controllers)/sizeof(controllers[0]); i++) { if ((controllers[i].vendor == vendor) && (controllers[i].device == device)) { ctrl.index = i; @@ -3682,8 +4120,10 @@ void find_controller(void) /* Don't enable ECC polling by default unless it has * been well tested. */ - set_ecc_polling(-1); + //set_ecc_polling(-1); print_memory_controller(); + + if(imc_type) { print_dmi_startup_info(); } } @@ -3694,6 +4134,7 @@ void poll_errors(void) } } +/* void set_ecc_polling(int val) { int tested = controllers[ctrl.index].tested; @@ -3708,5 +4149,5 @@ void set_ecc_polling(int val) cprint(LINE_INFO, COL_ECC, "off"); } } - +*/ |