From 72a02223e5778a2038252f611d6d0181f111b910 Mon Sep 17 00:00:00 2001 From: Michael Brown Date: Fri, 18 Sep 2009 04:36:57 +0100 Subject: [import] Import version 1.20 http://www.memtest.org/download/1.20/memtest86+-1.20.tar.gz --- changelog | 18 ++ controller.c | 186 ++++++++++++++++++-- ecount | 544 ----------------------------------------------------------- head.S | 5 + init.c | 55 ++++-- main.c | 7 +- precomp.bin | Bin 82724 -> 86980 bytes test.c | 11 +- test.h | 2 + 9 files changed, 255 insertions(+), 573 deletions(-) create mode 100644 changelog delete mode 100644 ecount diff --git a/changelog b/changelog new file mode 100644 index 0000000..8fb6bb4 --- /dev/null +++ b/changelog @@ -0,0 +1,18 @@ +- Added advanced support for Intel Grantsdale (i915) +- Added advanced support for Intel Alderwood (i925) +- Added advanced support for VIA K8T800 Pro +- Added support for Prescott core E0 +- Added support for Cyrix III CPU +- Added support for VIA C3 Samuel2/Ezra/Nehemiah CPU +- Added detection for VIA CLE266 and PLE133 Chipset +- Added support for .5 FID for AMD K8 +- Complete rewrite of the Cool 'n Quiet core +- Fixed a bug with K8 > 2.2 GHz +- Fixed a bug with test #12 (no kb input check) +- Removed the KTxxx (K7) advanced detection completely +- Removed Bit Fade Test from the test batch + (Can still be run standalone) +- Fixed a bug with VIA VT82C693A/694X detection + + + diff --git a/controller.c b/controller.c index 049cbb0..923a9e5 100644 --- a/controller.c +++ b/controller.c @@ -503,6 +503,25 @@ static void setup_i875(void) } +static void setup_i925(void) +{ + + // Activate MMR I/O + ulong dev0;//, drt; + //long *ptr; + + // Current stepping of i925X does not support ECC + ctrl.cap = ECC_CORRECT; + ctrl.mode = ECC_NONE; + + pci_conf_read( 0, 0, 0, 0x54, 4, &dev0); + dev0 = dev0 | 0x10000000; + pci_conf_write( 0, 0, 0, 0x54, 4, dev0); + + +} + + static void poll_i875(void) { unsigned long errsts; @@ -704,7 +723,7 @@ static void poll_i860(void) /* --------------------------------------------------------------------- */ -static int amd64cm[] = {0x0, 0x0, 0x0, 0x0, 0x0, 0x2, 0x4, 0x6, 0xB, 0xA, 0xC, 0xE, 0x10, 0x12, 0x14}; +static int amd64cm[] = {0x0, 0x0, 0x0, 0x0, 0x0, 0x2, 0x4, 0x6, 0x8, 0xA, 0xC, 0xE, 0x10, 0x12, 0x14, 0x16}; static float athloncoef[] = {11, 11.5, 12.0, 12.5, 5.0, 5.5, 6.0, 6.5, 7.0, 7.5, 8.0, 8.5, 9.0, 9.5, 10.0, 10.5}; static float athloncoef2[] = {12, 19.0, 12.0, 20.0, 13.0, 13.5, 14.0, 21.0, 15.0, 22, 16.0, 16.5, 17.0, 18.0, 23.0, 24.0}; @@ -712,19 +731,26 @@ static void poll_fsb_amd64(void) { unsigned int mcgsrl; unsigned int mcgsth; - unsigned long temp, temp2; + unsigned long fid, temp, temp2; unsigned long dramchr; double clockratio; double dramclock; int i; - int coef; + float coef; coef = 10; /* First, got the FID by MSR */ + /* First look if Cool 'n Quiet is supported to choose the right msr */ + if (((cpu_id.pwrcap >> 1) & 1) == 1) { + rdmsr(0xc0010042, mcgsrl, mcgsth); + fid = (mcgsrl& 0x1F); + } else { rdmsr(0xc0010015, mcgsrl, mcgsth); - temp = ((mcgsrl >> 24)& 0x0F); + fid = ((mcgsrl >> 24)& 0x1F); + } + + temp = fid & 0x1E; - for(i = 4; i < sizeof(amd64cm)/sizeof(amd64cm[0]); i++) { if (amd64cm[i] == temp) { coef = i; @@ -732,6 +758,9 @@ static void poll_fsb_amd64(void) { } } + /* Support for .5 coef */ + if ((fid & 1) == 1) { coef = coef + 0.5; } + /* Next, we need the clock ratio */ pci_conf_read(0, 24, 2, 0x94, 4, &dramchr); temp2 = (dramchr >> 20) & 0x7; @@ -763,6 +792,48 @@ static void poll_fsb_amd64(void) { } +static void poll_fsb_i925(void) { + + double dramclock, dramratio, fsb; + unsigned int msr_lo, msr_hi; + unsigned long mchcfg, dev0; + int coef; + long *ptr; + + /* Find multiplier (by MSR) */ + rdmsr(0x2C, msr_lo, msr_hi); + coef = (msr_lo >> 24) & 0x1F; + fsb = ((extclock /1000) / coef); + + /* Find dramratio */ + pci_conf_read( 0, 0, 0, 0x44, 4, &dev0); + ptr=(long*)(dev0+0x112); + mchcfg = *ptr & 0xFFFF; + dramratio = 1; + mchcfg = (mchcfg >> 12)&3; + + if (mchcfg == 2) { dramratio = 1; } + else if (mchcfg == 3) { dramratio = 1.33334; } + else if (mchcfg == 1) { dramratio = 0.66667; } + + // Compute RAM Frequency + fsb = ((extclock /1000) / coef); + dramclock = fsb * dramratio; + + // Print DRAM Freq + print_fsb_info(dramclock, "RAM : "); + + /* Print FSB (only if ECC is not enabled) */ + + cprint(LINE_CPU+4, col +1, "- FSB : "); + col += 9; + dprint(LINE_CPU+4, col, fsb, 3,0); + col += 3; + cprint(LINE_CPU+4, col +1, "Mhz"); + col += 4; + +} + static void poll_fsb_i875(void) { double dramclock, dramratio, fsb; @@ -974,6 +1045,88 @@ static void poll_fsb_nf2(void) { /* ------------------ Here the code for Timings detection ------------------ */ /* ------------------------------------------------------------------------- */ +static void poll_timings_i925(void) { + + ulong dev0, mch, drt, drc, dcc, temp; + long *ptr; + + + //Read Offset 9C + pci_conf_read( 0, 0, 0, 0x9C, 1, &mch); + + //Now, read MMR Base Address + pci_conf_read( 0, 0, 0, 0x44, 4, &dev0); + + //Set pointer for DRT + ptr=(long*)(dev0+0x114); + drt = *ptr & 0xFFFFFFFF; + + //Set pointer for DRC + ptr=(long*)(dev0+0x120); + drc = *ptr & 0xFFFFFFFF; + + //Set pointer for DCC + ptr=(long*)(dev0+0x200); + dcc = *ptr & 0xFFFFFFFF; + + //Determine DDR or DDR-II + + if ((drc & 3) == 2) { + cprint(LINE_CPU+4, col +1, "- Type : DDR-II"); + } else { + cprint(LINE_CPU+4, col +1, "- Type : DDR-I"); + } + + // Now, detect timings + cprint(LINE_CPU+5, col2 +1, "/ CAS : "); + col2 += 9; + + // CAS Latency (tCAS) + temp = ((drt >> 8)& 0x3); + + if ((drc & 3) == 2){ + // Timings DDR-II + if (temp == 0x0) { cprint(LINE_CPU+5, col2, "5-"); } + else if (temp == 0x1) { cprint(LINE_CPU+5, col2, "4-"); } + else { cprint(LINE_CPU+5, col2, "3-"); } + } else { + // Timings DDR-I + if (temp == 0x0) { cprint(LINE_CPU+5, col2, "3-"); } + else if (temp == 0x1) { cprint(LINE_CPU+5, col2, "2.5-"); col2 +=2;} + else { cprint(LINE_CPU+5, col2, "2-"); } + } + col2 +=2; + + // RAS-To-CAS (tRCD) + temp = ((drt >> 4)& 0x3); + if (temp == 0x0) { cprint(LINE_CPU+5, col2, "2-"); } + else if (temp == 0x1) { cprint(LINE_CPU+5, col2, "3-"); } + else if (temp == 0x2) { cprint(LINE_CPU+5, col2, "4-"); } + else { cprint(LINE_CPU+5, col2, "5-"); } + col2 +=2; + + // RAS Precharge (tRP) + temp = (drt&0x3); + if (temp == 0x0) { cprint(LINE_CPU+5, col2, "2-"); } + else if (temp == 0x1) { cprint(LINE_CPU+5, col2, "3-"); } + else if (temp == 0x2) { cprint(LINE_CPU+5, col2, "4-"); } + else { cprint(LINE_CPU+5, col2, "5-"); } + col2 +=2; + + // RAS Active to precharge (tRAS) + temp = ((drt >> 20)& 0xF); + dprint(LINE_CPU+5, col2, temp , 1 ,0); + (temp < 10)?(col2 += 1):(col2 += 2); + + cprint(LINE_CPU+5, col2+1, "/"); col2 +=2; + + temp = (dcc&0x3); + if (temp == 1) { cprint(LINE_CPU+5, col2, " Dual Channel (Asymmetric)"); } + else if (temp == 2) { cprint(LINE_CPU+5, col2, " Dual Channel (Interleaved)"); } + else { cprint(LINE_CPU+5, col2, " Single Channel (64 bits)"); } + + +} static void poll_timings_i875(void) { @@ -1290,6 +1443,7 @@ static struct pci_memory_controller controllers[] = { { 0x1022, 0x7006, "AMD 751", 0, poll_fsb_nothing, poll_timings_nothing, setup_amd751, poll_amd751 }, { 0x1022, 0x700c, "AMD 762", 0, poll_fsb_nothing, poll_timings_nothing, setup_amd76x, poll_amd76x }, { 0x1022, 0x700e, "AMD 761", 0, poll_fsb_nothing, poll_timings_nothing, setup_amd76x, poll_amd76x }, + { 0x1022, 0x1100, "AMD 8000", 0, poll_fsb_amd64, poll_timings_amd64, setup_amd64, poll_amd64 }, { 0x1022, 0x7454, "AMD 8000", 0, poll_fsb_amd64, poll_timings_amd64, setup_amd64, poll_amd64 }, /* Motorola */ @@ -1331,7 +1485,7 @@ static struct pci_memory_controller controllers[] = { { 0x10de, 0x01A4, "nVidia nForce", 0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing }, { 0x10de, 0x01E0, "nVidia nForce2 SPP", 0, poll_fsb_nf2, poll_timings_nf2, setup_nothing, poll_nothing }, { 0x10de, 0x00D1, "nVidia nForce3", 0, poll_fsb_amd64, poll_timings_amd64, setup_amd64, poll_amd64 }, - { 0x10de, 0x00E1, "nVidia nForce3-S", 0, poll_fsb_amd64, poll_timings_amd64, setup_amd64, poll_amd64 }, + { 0x10de, 0x00E1, "nForce3 250", 0, poll_fsb_amd64, poll_timings_amd64, setup_amd64, poll_amd64 }, /* VIA */ { 0x1106, 0x0305, "VIA KT133/KT133A", 0, poll_fsb_amd32, poll_timings_nothing, setup_nothing, poll_nothing }, @@ -1340,18 +1494,20 @@ static struct pci_memory_controller controllers[] = { { 0x1106, 0x0585, "vt82c585", 0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing }, { 0x1106, 0x0595, "vt82c595", 0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing }, { 0x1106, 0x0597, "vt82c597", 0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing }, - { 0x1106, 0x0598, "vt82c598", 0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing }, - { 0x1106, 0x0691, "vt82c691", 0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing }, - { 0x1106, 0x0693, "vt82c693", 0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing }, - { 0x1106, 0x0694, "vt82c694", 0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing }, - { 0x1106, 0x3099, "VIA KT266(A)/KT333", 0, poll_fsb_amd32, poll_timings_nothing, setup_nothing, poll_nothing }, - { 0x1106, 0x3189, "VIA KT400(A)/600", 0, poll_fsb_amd32, poll_timings_nothing, setup_nothing, poll_nothing }, + { 0x1106, 0x0598, "VT82C598", 0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing }, + { 0x1106, 0x0691, "VT82C691/693A/694X", 0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing }, + { 0x1106, 0x0693, "VT82C693", 0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing }, + { 0x1106, 0x0601, "VIA PLE133", 0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing }, + { 0x1106, 0x3099, "VIA KT266(A)/KT333", 0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing }, + { 0x1106, 0x3189, "VIA KT400(A)/600", 0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing }, { 0x1106, 0x3205, "VIA KM400", 0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing }, { 0x1106, 0x3116, "VIA KM266", 0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing }, { 0x1106, 0x3156, "VIA KN266", 0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing }, + { 0x1106, 0x3123, "VIA CLE266", 0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing }, { 0x1106, 0x0198, "VIA PT800", 0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing }, { 0x1106, 0x3258, "VIA PT880", 0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing }, { 0x1106, 0x3188, "VIA K8T800", 0, poll_fsb_amd64, poll_timings_amd64, setup_amd64, poll_amd64 }, + { 0x1106, 0x0282, "VIA K8T800Pro", 0, poll_fsb_amd64, poll_timings_amd64, setup_amd64, poll_amd64 }, /* Serverworks */ { 0x1166, 0x0008, "CNB20HE", 0, poll_fsb_nothing, poll_timings_nothing, setup_cnb20, poll_nothing }, @@ -1367,8 +1523,6 @@ static struct pci_memory_controller controllers[] = { { 0x8086, 0x2560, "Intel i845E/G/PE/GE", 0, poll_fsb_p4, poll_timings_nothing, setup_i845, poll_i845 }, { 0x8086, 0x2500, "Intel i820", 0, poll_fsb_nothing, poll_timings_nothing, setup_i820, poll_i820 }, { 0x8086, 0x2530, "Intel i850", 0, poll_fsb_p4, poll_timings_nothing, setup_i850, poll_i850 }, - { 0x8086, 0x2570, "Intel i848/i865", 0, poll_fsb_i875, poll_timings_i875, setup_i875, poll_nothing }, - { 0x8086, 0x2578, "Intel i875P", 0, poll_fsb_i875, poll_timings_i875, setup_i875, poll_i875 }, { 0x8086, 0x2531, "Intel i860", 1, poll_fsb_nothing, poll_timings_nothing, setup_i860, poll_i860 }, { 0x8086, 0x7030, "Intel i430vx", 0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing }, { 0x8086, 0x7120, "Intel i810", 0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing }, @@ -1383,9 +1537,13 @@ static struct pci_memory_controller controllers[] = { { 0x8086, 0x2540, "Intel E7500", 1, poll_fsb_p4, poll_timings_nothing, setup_iE7xxx, poll_iE7xxx }, { 0x8086, 0x254C, "Intel E7501", 0, poll_fsb_p4, poll_timings_nothing, setup_iE7xxx, poll_iE7xxx }, { 0x8086, 0x255d, "Intel E7205", 0, poll_fsb_p4, poll_timings_nothing, setup_iE7xxx, poll_iE7xxx }, + { 0x8086, 0x2570, "Intel i848/i865", 0, poll_fsb_i875, poll_timings_i875, setup_i875, poll_nothing }, + { 0x8086, 0x2578, "Intel i875P", 0, poll_fsb_i875, poll_timings_i875, setup_i875, poll_i875 }, { 0x8086, 0x2550, "Intel E7505", 0, poll_fsb_p4, poll_timings_nothing, setup_iE7xxx, poll_iE7xxx }, { 0x8086, 0x3580, "Intel ", 0, poll_fsb_i855, poll_timings_i852, setup_nothing, poll_nothing }, { 0x8086, 0x3340, "Intel i855PM", 0, poll_fsb_i855, poll_timings_i855, setup_nothing, poll_nothing }, + { 0x8086, 0x2580, "Intel i915P/G", 0, poll_fsb_i925, poll_timings_i925, setup_i925, poll_nothing }, + { 0x8086, 0x2584, "Intel i925X", 0, poll_fsb_i925, poll_timings_i925, setup_i925, poll_nothing }, }; static void print_memory_controller(void) diff --git a/ecount b/ecount deleted file mode 100644 index 0c2ce9b..0000000 --- a/ecount +++ /dev/null @@ -1,544 +0,0 @@ -config.c:48: cprint(POP_Y+3+v->cache_flag, POP_X+5, ">"); -config.c:54: v->cache_flag = 0; -config.c:55: set_cache(tseq[v->test].cache); -config.c:61: v->cache_flag = 1; -config.c:62: if (tseq[v->test].cache == 0) { -config.c:71: v->cache_flag = 2; -config.c:72: if (tseq[v->test].cache == 1) { -config.c:97: if (v->testsel < 0) { -config.c:98: cprint(POP_Y+3+v->xtst_flag, POP_X+5, ">"); -config.c:107: v->xtst_flag = 0; -config.c:108: if (v->test > DEFTESTS) { -config.c:111: v->testsel = -1; -config.c:118: v->xtst_flag = 1; -config.c:119: if (v->test <= DEFTESTS) { -config.c:122: v->testsel = -1; -config.c:129: v->xtst_flag = 2; -config.c:130: v->testsel = -1; -config.c:149: v->testsel = i; -config.c:183: aprint(POP_Y+4, POP_X+13, v->plim_lower); -config.c:187: if (page + 1 <= v->plim_upper) { -config.c:188: v->plim_lower = page; -config.c:202: aprint(POP_Y+4, POP_X+13, v->plim_upper); -config.c:206: if (page - 1 >= v->plim_lower) { -config.c:207: v->plim_upper = page; -config.c:216: v->plim_lower = 0; -config.c:217: v->plim_upper = v->pmap[v->msegs - 1].end; -config.c:237: if (v->e820_nr) { -config.c:241: cprint(POP_Y+2+v->memsz_mode, POP_X+5, ">"); -config.c:245: if (v->memsz_mode == SZ_MODE_BIOS) { -config.c:255: v->memsz_mode = SZ_MODE_BIOS; -config.c:258: v->test = 0; -config.c:259: v->pass = 0; -config.c:260: v->total_ticks = 0; -config.c:265: v->memsz_mode = SZ_MODE_BIOS_RES; -config.c:268: v->test = 0; -config.c:269: v->pass = 0; -config.c:270: v->total_ticks = 0; -config.c:275: v->memsz_mode = SZ_MODE_PROBE; -config.c:278: v->test = 0; -config.c:279: v->pass = 0; -config.c:280: v->total_ticks = 0; -config.c:315: cprint(POP_Y+3+v->printmode, POP_X+5, ">"); -config.c:321: v->printmode=PRINTMODE_ADDRESSES; -config.c:322: v->eadr = 0; -config.c:327: v->printmode=PRINTMODE_PATTERNS; -config.c:333: v->printmode=PRINTMODE_NONE; -config.c:437: v->selected_pages = 0; -config.c:438: for (i=0; i< v->msegs; i++) { -config.c:440: if (v->pmap[i].start >= v->plim_lower && -config.c:441: v->pmap[i].end <= v->plim_upper) { -config.c:442: v->selected_pages += (v->pmap[i].end - v->pmap[i].start); -config.c:446: if (v->pmap[i].start < v->plim_lower) { -config.c:448: if (v->pmap[i].end < v->plim_lower) { -config.c:453: if (v->pmap[i].end > v->plim_upper) { -config.c:454: v->selected_pages += -config.c:455: v->plim_upper - v->plim_lower; -config.c:458: v->selected_pages += -config.c:459: (v->pmap[i].end - v->plim_lower); -config.c:464: if (v->pmap[i].end > v->plim_upper) { -config.c:466: if (v->pmap[i].start > v->plim_upper) { -config.c:470: v->selected_pages += -config.c:471: (v->plim_upper - v->pmap[i].start); -controller.c~:112: v->pmap[i].start = (START_ADR + (1 << 12) - 1) >> 12; -controller.c~:113: p = (unsigned long *)(v->pmap[i].start << 12); -controller.c~:123: v->pmap[i].end = SKIP_START >> 12; -controller.c~:126: v->pmap[i].start = 0; -controller.c~:132: v->pmap[i].end = ((unsigned long)p) >> 12; -controller.c~:150: v->pmap[i].start = ((unsigned long)p) >> 12; -controller.c~:168: if (v->pmap[i].start) { -controller.c~:169: v->pmap[i].end = ((unsigned long)m_lim) >> 12; -controller.c~:171: v->pmap[i].start = 0; -controller.c~:173: v->msegs = i; -controller.c~:174: v->ecc_cap = ECC_UNKNOWN; -controller.c~:175: v->ecc_mode = ECC_UNKNOWN; -controller.c~:182: v->ecc_cap = ECC_NONE; -controller.c~:183: v->ecc_mode = ECC_NONE; -controller.c~:204: v->ecc_cap = ECC_CORRECT; -controller.c~:205: v->ecc_mode = (dram_status & (1 << 2))?ECC_CORRECT: ECC_NONE; -controller.c~:255: v->ecc_cap = ECC_CORRECT; -controller.c~:256: v->ecc_mode = ddim[(ecc_mode_status >> 10)&3]; -controller.c~:311: v->pmap[0].start = 0x000000; -controller.c~:312: v->pmap[0].end = 0x0000a0; -controller.c~:313: v->pmap[1].start = 0x000100; -controller.c~:314: v->pmap[1].end = 0x0fc000; -controller.c~:315: v->pmap[2].start = 0x100000; -controller.c~:316: v->pmap[2].end = 0x180000; -controller.c~:317: v->msegs = 3; -controller.c~:320: v->ecc_cap = ECC_CORRECT; -controller.c~:338: v->ecc_cap = ECC_CORRECT; -controller.c~:339: v->ecc_mode = ddim[(nbxcfg >> 7)&3]; -controller.c~:382: v->ecc_cap = ECC_CORRECT; -controller.c~:383: v->ecc_mode = ddim[(mchcfg >> 7)&3]; -controller.c~:427: v->ecc_cap = ECC_CORRECT; -controller.c~:428: v->ecc_mode = ddim[(drc >> 20)&3]; -controller.c~:469: v->ecc_cap = ECC_CORRECT; -controller.c~:470: v->ecc_mode = ddim[(mchcfg >> 7)&3]; -controller.c~:509: v->ecc_cap = ECC_CORRECT; -controller.c~:510: v->ecc_mode = ddim[(mchcfg >> 7)&3]; -controller.c~:553: v->ecc_cap = ECC_CORRECT; -controller.c~:554: v->ecc_mode = ddim[(drc >> 7)&3]; -controller.c~:683: for(i = 0; i < sizeof(v->controller_name); i++) { -controller.c~:686: v->controller_name[i] = ch; -controller.c~:690: v->controller_name[sizeof(v->controller_name) -1] = '\0'; -init.c:74: v->memsz_mode = SZ_MODE_BIOS; -init.c:76: v->firmware = FIRMWARE_UNKNOWN; -init.c:77: if ((v->firmware == FIRMWARE_UNKNOWN) && -init.c:78: (v->memsz_mode != SZ_MODE_PROBE)) { -init.c:80: v->firmware = FIRMWARE_LINUXBIOS; -init.c:83: v->firmware = FIRMWARE_PCBIOS; -init.c:95: v->test = 0; -init.c:96: v->testsel = -1; -init.c:97: v->msg_line = LINE_SCROLL-1; -init.c:98: v->scroll_start = v->msg_line * 160; -init.c:103: aprint(LINE_CPU+3, 10, v->test_pages); -init.c:108: if (v->rdtsc) { -init.c:128: v->printmode=PRINTMODE_ADDRESSES; -init.c:129: v->numpatn=0; -init.c:138: if (!v->pae) -init.c:157: if (!v->pae) -init.c:192: if (!v->pae || (window >= 32)) { -init.c:266: v->rdtsc = 0; -init.c:267: v->pae = 0; -init.c:323: v->pae = 1; -init.c:652: if ((1 + (i * 2)) > (v->plim_upper << 2)) { -init.c:653: i = ((v->plim_upper <<2) - 1) / 2; -init.c:661: asm __volatile__ ("rdtsc":"=a" (v->startl),"=d" (v->starth)); -init.c:662: v->snapl = v->startl; -init.c:663: v->snaph = v->starth; -init.c:664: v->rdtsc = 1; -init.c:673: mem_top = v->pmap[v->msegs -1].end; -init.c:722: v->clks_msec = end_low/48; -init.c:723: return(v->clks_msec); -init.c:824: return((v->clks_msec)/end_low); -init.c~:61: v->memsz_mode = SZ_MODE_BIOS; -init.c~:63: v->firmware = FIRMWARE_UNKNOWN; -init.c~:64: if ((v->firmware == FIRMWARE_UNKNOWN) && -init.c~:65: (v->memsz_mode != SZ_MODE_PROBE)) { -init.c~:67: v->firmware = FIRMWARE_LINUXBIOS; -init.c~:70: v->firmware = FIRMWARE_PCBIOS; -init.c~:76: v->test = 0; -init.c~:77: v->testsel = -1; -init.c~:78: v->msg_line = LINE_SCROLL-1; -init.c~:79: v->scroll_start = v->msg_line * 160; -init.c~:84: aprint(LINE_CPU+3, 10, v->test_pages); -init.c~:88: if (v->rdtsc) { -init.c~:109: v->printmode=PRINTMODE_ADDRESSES; -init.c~:110: v->numpatn=0; -init.c~:119: if (!v->pae) -init.c~:138: if (!v->pae) -init.c~:173: if (!v->pae || (window >= 32)) { -init.c~:247: v->rdtsc = 0; -init.c~:248: v->pae = 0; -init.c~:304: v->pae = 1; -init.c~:633: if ((1 + (i * 2)) > (v->plim_upper << 2)) { -init.c~:634: i = ((v->plim_upper <<2) - 1) / 2; -init.c~:642: asm __volatile__ ("rdtsc":"=a" (v->startl),"=d" (v->starth)); -init.c~:643: v->snapl = v->startl; -init.c~:644: v->snaph = v->starth; -init.c~:645: v->rdtsc = 1; -init.c~:654: mem_top = v->pmap[v->msegs -1].end; -init.c~:703: v->clks_msec = end_low/48; -init.c~:704: return(v->clks_msec); -init.c~:805: return((v->clks_msec)/end_low); -lib.c:102: if (v->msg_line < 23) { -lib.c:103: v->msg_line++; -lib.c:401: if (v->cache_flag) { -lib.c:409: if (v->cache_flag) { -lib.c~:102: if (v->msg_line < 23) { -lib.c~:103: v->msg_line++; -lib.c~:421: if (v->cache_flag) { -lib.c~:429: if (v->cache_flag) { -main.c:143: if (v->firsttime == 0) { -main.c:150: v->firsttime = 1; -main.c:160: if (map_page(v->map[0].pbase_addr) < 0) { -main.c:165: lo = page_of(v->map[0].start); -main.c:166: hi = page_of(v->map[segs -1].end); -main.c:170: aprint(LINE_RANGE, COL_MID+23, v->selected_pages); -main.c:183: :"b" (v->snapl), "c" (v->snaph) -main.c:187: t = h * ((unsigned)0xffffffff / v->clks_msec) / 1000; -main.c:188: t += (l / v->clks_msec) / 1000; -main.c:199: asm __volatile__ ("rdtsc":"=a" (v->snapl),"=d" (v->snaph)); -main.c:204: if (v->testsel < 0) { -main.c:205: switch(v->xtst_flag) { -main.c:207: if (v->test > DEFTESTS) { -main.c:212: if (v->test <= DEFTESTS) { -main.c:220: if ((v->cache_flag == 1 && tseq[v->test].cache == 0) || -main.c:221: (v->cache_flag == 2 && tseq[v->test].cache == 1)) { -main.c:225: v->test = v->testsel; -main.c:227: dprint(LINE_TST, COL_MID+6, v->test, 2, 1); -main.c:228: cprint(LINE_TST, COL_MID+9, tseq[v->test].msg); -main.c:229: set_cache(tseq[v->test].cache); -main.c:235: len = v->map[i].end - v->map[i].start; -main.c:239: test_ticks = find_ticks_for_test(chunks, v->test); -main.c:241: v->tptr = 0; -main.c:243: switch(tseq[v->test].pat) { -main.c:249: movinv1(tseq[v->test].iter,p1,p2); -main.c:255: movinv1(tseq[v->test].iter,p1,p2); -main.c:263: movinv1(tseq[v->test].iter,p1,p2); -main.c:269: movinv1(tseq[v->test].iter,p1,p2); -main.c:276: movinv32(tseq[v->test].iter,p1, 1, 0x80000000, 0, i); -main.c:278: movinv32(tseq[v->test].iter,~p1, 0xfffffffe, -main.c:288: modtst(i, tseq[v->test].iter, p1, p2); -main.c:294: modtst(i, tseq[v->test].iter, p1,p2); -main.c:305: modtst(i, tseq[v->test].iter, p1, p2); -main.c:311: modtst(i, tseq[v->test].iter, p1, p2); -main.c:326: block_move(tseq[v->test].iter); -main.c:350: if (v->pmap[v->msegs-1].end > -main.c:370: v->test++; -main.c:381: if (tseq[v->test].msg == NULL || v->testsel >= 0) { -main.c:382: v->pass++; -main.c:383: dprint(LINE_INFO, COL_PASS, v->pass, 5, 0); -main.c:384: v->test = 0; -main.c:385: v->total_ticks = 0; -main.c:386: v->pptr = 0; -main.c:401: v->firsttime = 0; -main.c:415: v->pptr = 0; -main.c:423: len = v->map[i].end - v->map[i].start; -main.c:429: for (v->pass_ticks=0, i=0; tseq[i].msg != NULL; i++) { -main.c:432: if (v->testsel >= 0) { -main.c:433: if (i != v->testsel) { -main.c:437: if (v->xtst_flag == 0 && i > DEFTESTS) { -main.c:440: if (v->xtst_flag == 1 && i <= DEFTESTS) { -main.c:443: if ((v->cache_flag == 1 && tseq[i].cache == 0) || -main.c:444: (v->cache_flag == 2 && tseq[i].cache == 1)) { -main.c:448: v->pass_ticks += find_ticks_for_test(chunks, i); -main.c:474: if (wstart < v->plim_lower) { -main.c:475: wstart = v->plim_lower; -main.c:477: if (wend > v->plim_upper) { -main.c:478: wend = v->plim_upper; -main.c:484: for (i=0; i< v->msegs; i++) { -main.c:486: start = v->pmap[i].start; -main.c:487: end = v->pmap[i].end; -main.c:508: hprint(LINE_SCROLL+(2*i), 46, v->plim_lower); -main.c:510: hprint(LINE_SCROLL+(2*i), 56, v->plim_upper); -main.c:520: hprint(LINE_SCROLL+(2*i+1), 24, v->pmap[i].start); -main.c:522: hprint(LINE_SCROLL+(2*i+1), 34, v->pmap[i].end); -main.c:536: v->map[segs].pbase_addr = start; -main.c:537: v->map[segs].start = mapping(start); -main.c:538: v->map[segs].end = emapping(end); -memsize.c:31: v->reserved_pages = 0; -memsize.c:32: v->test_pages = 0; -memsize.c:36: v->ext_mem_k = mem_info.e88_mem_k; -memsize.c:37: v->alt_mem_k = mem_info.e801_mem_k; -memsize.c:38: v->e820_nr = mem_info.e820_nr; -memsize.c:40: v->e820[i].addr = mem_info.e820[i].addr; -memsize.c:41: v->e820[i].size = mem_info.e820[i].size; -memsize.c:42: v->e820[i].type = mem_info.e820[i].type; -memsize.c:45: switch (v->memsz_mode) { -memsize.c:62: v->plim_lower = 0; -memsize.c:63: v->plim_upper = v->pmap[v->msegs-1].end; -memsize.c:66: aprint(LINE_INFO, COL_RESERVED, v->reserved_pages); -memsize.c:71: if (v->firmware == FIRMWARE_PCBIOS) { -memsize.c:74: else if (v->firmware == FIRMWARE_LINUXBIOS) { -memsize.c:85: for(i = 0; i < v->msegs; i++) { -memsize.c:88: if (v->pmap[i].start > v->pmap[j].start) { -memsize.c:96: temp = v->pmap[i]; -memsize.c:97: memmove(&v->pmap[j], &v->pmap[j+1], -memsize.c:99: v->pmap[j] = temp; -memsize.c:108: for (i=0; i < v->e820_nr; i++) { -memsize.c:110: if (v->e820[i].type != E820_RAM) { -memsize.c:113: end = v->e820[i].addr; -memsize.c:114: end += v->e820[i].size; -memsize.c:115: v->pmap[n].start = (v->e820[i].addr + 4095) >> 12; -memsize.c:116: v->pmap[n].end = end >> 12; -memsize.c:117: v->test_pages += v->pmap[n].end - v->pmap[n].start; -memsize.c:120: v->msegs = n; -memsize.c:130: nr = sanitize_e820_map(v->e820, nm, v->e820_nr, res); -memsize.c:160: v->pmap[n].start = (start + 4095) >> 12; -memsize.c:161: v->pmap[n].end = end >> 12; -memsize.c:162: v->test_pages += v->pmap[n].end - v->pmap[n].start; -memsize.c:165: v->reserved_pages += nm[i].size >> 12; -memsize.c:168: v->msegs = n; -memsize.c:183: if (v->alt_mem_k < v->ext_mem_k) { -memsize.c:184: mem_size = v->ext_mem_k; -memsize.c:187: mem_size = v->alt_mem_k; -memsize.c:191: v->pmap[0].start = 0; -memsize.c:192: v->pmap[0].end = RES_START >> 12; -memsize.c:193: v->test_pages = RES_START >> 12; -memsize.c:196: v->pmap[1].start = (RES_END + 4095) >> 12; -memsize.c:197: v->pmap[1].end = (mem_size + 1024) >> 2; -memsize.c:198: v->test_pages += mem_size >> 2; -memsize.c:199: v->msegs = 2; -memsize.c:394: v->pmap[i].start = ((ulong)&_end + (1 << 12) - 1) >> 12; -memsize.c:395: p = (ulong *)(v->pmap[i].start << 12); -memsize.c:404: v->pmap[i].end = RES_START >> 12; -memsize.c:405: v->test_pages += (v->pmap[i].end - v->pmap[i].start); -memsize.c:408: v->pmap[i].start = 0; -memsize.c:414: v->pmap[i].end = ((ulong)p) >> 12; -memsize.c:415: v->test_pages += (v->pmap[i].end - v->pmap[i].start); -memsize.c:417: v->pmap[i].start = 0; -memsize.c:433: v->pmap[i].start = (ulong)p >> 12; -memsize.c:451: if (v->pmap[i].start) { -memsize.c:452: v->pmap[i].end = m_lim >> 12; -memsize.c:453: v->test_pages += (v->pmap[i].end - v->pmap[i].start); -memsize.c:456: v->msegs = i; -memsize.c~:31: v->reserved_pages = 0; -memsize.c~:32: v->test_pages = 0; -memsize.c~:36: v->ext_mem_k = mem_info.e88_mem_k; -memsize.c~:37: v->alt_mem_k = mem_info.e801_mem_k; -memsize.c~:38: v->e820_nr = mem_info.e820_nr; -memsize.c~:40: v->e820[i].addr = mem_info.e820[i].addr; -memsize.c~:41: v->e820[i].size = mem_info.e820[i].size; -memsize.c~:42: v->e820[i].type = mem_info.e820[i].type; -memsize.c~:45: switch (v->memsz_mode) { -memsize.c~:62: v->plim_lower = 0; -memsize.c~:63: v->plim_upper = v->pmap[v->msegs-1].end; -memsize.c~:66: dprint(LINE_INFO, 19, v->reserved_pages << 2, 7, 0); -memsize.c~:71: if (v->firmware == FIRMWARE_PCBIOS) { -memsize.c~:74: else if (v->firmware == FIRMWARE_LINUXBIOS) { -memsize.c~:85: for(i = 0; i < v->msegs; i++) { -memsize.c~:88: if (v->pmap[i].start > v->pmap[j].start) { -memsize.c~:96: temp = v->pmap[i]; -memsize.c~:97: memmove(&v->pmap[j], &v->pmap[j+1], -memsize.c~:99: v->pmap[j] = temp; -memsize.c~:108: for (i=0; i < v->e820_nr; i++) { -memsize.c~:110: if (v->e820[i].type != E820_RAM) { -memsize.c~:113: end = v->e820[i].addr; -memsize.c~:114: end += v->e820[i].size; -memsize.c~:115: v->pmap[n].start = (v->e820[i].addr + 4095) >> 12; -memsize.c~:116: v->pmap[n].end = end >> 12; -memsize.c~:117: v->test_pages += v->pmap[n].end - v->pmap[n].start; -memsize.c~:120: v->msegs = n; -memsize.c~:130: nr = sanitize_e820_map(v->e820, nm, v->e820_nr, res); -memsize.c~:160: v->pmap[n].start = (start + 4095) >> 12; -memsize.c~:161: v->pmap[n].end = end >> 12; -memsize.c~:162: v->test_pages += v->pmap[n].end - v->pmap[n].start; -memsize.c~:165: v->reserved_pages += nm[i].size >> 12; -memsize.c~:168: v->msegs = n; -memsize.c~:183: if (v->alt_mem_k < v->ext_mem_k) { -memsize.c~:184: mem_size = v->ext_mem_k; -memsize.c~:187: mem_size = v->alt_mem_k; -memsize.c~:191: v->pmap[0].start = 0; -memsize.c~:192: v->pmap[0].end = RES_START >> 12; -memsize.c~:193: v->test_pages = RES_START >> 12; -memsize.c~:196: v->pmap[1].start = (RES_END + 4095) >> 12; -memsize.c~:197: v->pmap[1].end = (mem_size + 1024) >> 2; -memsize.c~:198: v->test_pages += mem_size >> 2; -memsize.c~:199: v->msegs = 2; -memsize.c~:394: v->pmap[i].start = ((ulong)&_end + (1 << 12) - 1) >> 12; -memsize.c~:395: p = (ulong *)(v->pmap[i].start << 12); -memsize.c~:404: v->pmap[i].end = RES_START >> 12; -memsize.c~:405: v->test_pages += (v->pmap[i].end - v->pmap[i].start); -memsize.c~:408: v->pmap[i].start = 0; -memsize.c~:414: v->pmap[i].end = ((ulong)p) >> 12; -memsize.c~:415: v->test_pages += (v->pmap[i].end - v->pmap[i].start); -memsize.c~:417: v->pmap[i].start = 0; -memsize.c~:433: v->pmap[i].start = (ulong)p >> 12; -memsize.c~:451: if (v->pmap[i].start) { -memsize.c~:452: v->pmap[i].end = m_lim >> 12; -memsize.c~:453: v->test_pages += (v->pmap[i].end - v->pmap[i].start); -memsize.c~:456: v->msegs = i; -patn.c:70: int i=v->numpatn; -patn.c:73: ulong tmpcost=combicost(v->patn[i].adr, v->patn[i].mask, adr1, mask1); -patn.c:86: ulong adr =v->patn[idx].adr; -patn.c:87: ulong mask=v->patn[idx].mask; -patn.c:89: v->patn[idx].adr ^= ~0L; // Never select idx -patn.c:91: v->patn[idx].adr = adr; -patn.c:103: combine (v->patn [newidx].adr, v->patn[newidx].mask, -patn.c:104: v->patn [ idx].adr, v->patn[ idx].mask, -patn.c:106: v->patn[newidx].adr =cadr; -patn.c:107: v->patn[newidx].mask=cmask; -patn.c:108: if (idx < --v->numpatn) { -patn.c:109: v->patn[idx].adr =v->patn[v->numpatn].adr; -patn.c:110: v->patn[idx].mask=v->patn[v->numpatn].mask; -patn.c:123: if (v->numpatn < BADRAM_MAXPATNS) { -patn.c:124: v->patn[v->numpatn].adr =adr; -patn.c:125: v->patn[v->numpatn].mask=DEFAULT_MASK; -patn.c:126: v->numpatn++; -patn.c:127: relocateiffree (v->numpatn-1); -patn.c:131: combine (v->patn [idx].adr, v->patn[idx].mask, -patn.c:133: v->patn[idx].adr =cadr; -patn.c:134: v->patn[idx].mask=cmask; -test.c:40: p = (ulong *)roundup((ulong)v->map[0].start, 0x1ffff); -test.c:45: end = v->map[segs-1].end; -test.c:72: if (v->pmap[v->msegs - 1].end > (0x800000 >> 12)) { -test.c:81: p = v->map[j].start; -test.c:84: end = v->map[j].end; -test.c:136: start = v->map[j].start; -test.c:137: end = v->map[j].end; -test.c:180: start = v->map[j].start; -test.c:181: end = v->map[j].end; -test.c:257: start = v->map[j].start; -test.c:258: end = v->map[j].end; -test.c:298: start = v->map[j].start; -test.c:299: end = v->map[j].end; -test.c:364: start = v->map[j].start; -test.c:365: end = v->map[j].end; -test.c:448: start = v->map[j].start; -test.c:449: end = v->map[j].end; -test.c:516: start = v->map[j].start; -test.c:517: end = v->map[j].end; -test.c:623: start = v->map[j].start; -test.c:624: end = v->map[j].end; -test.c:735: start = v->map[j].start; -test.c:736: end = v->map[j].end; -test.c:779: start = v->map[j].start; -test.c:780: end = v->map[j].end; -test.c:838: start = v->map[j].start; -test.c:839: end = v->map[j].end; -test.c:916: start = (ulong)v->map[j].start; -test.c:925: end = (ulong)v->map[j].end; -test.c:985: start = (ulong)v->map[j].start; -test.c:994: end = (ulong)v->map[j].end; -test.c:1052: start = (ulong)v->map[j].start; -test.c:1061: end = (ulong)v->map[j].end; -test.c:1139: if (v->printmode == PRINTMODE_ADDRESSES) { -test.c:1142: if ((ulong)adr == (ulong)v->eadr && xor == v->exor) { -test.c:1144: dprint(v->msg_line, 62, ++ecount, 5, 0); -test.c:1149: } else if (v->printmode == PRINTMODE_PATTERNS) { -test.c:1168: if (v->printmode == PRINTMODE_NONE) { -test.c:1184: if (v->printmode == PRINTMODE_NONE) { -test.c:1204: if (v->printmode == PRINTMODE_ADDRESSES) { -test.c:1206: } else if (v->printmode == PRINTMODE_PATTERNS) { -test.c:1226: ++(v->ecount); -test.c:1227: tseq[v->test].errors++; -test.c:1232: dprint(LINE_INFO, COL_ERR, v->ecount, 6, 0); -test.c:1248: dprint(v->msg_line, 0, v->test, 3, 0); -test.c:1249: dprint(v->msg_line, 4, v->pass, 5, 0); -test.c:1250: hprint(v->msg_line, 11, page); -test.c:1251: hprint2(v->msg_line, 19, offset, 3); -test.c:1252: cprint(v->msg_line, 22, " - . MB"); -test.c:1253: dprint(v->msg_line, 25, mb, 5, 0); -test.c:1254: dprint(v->msg_line, 31, ((page & 0xF)*10)/16, 1, 0); -test.c:1268: hprint(v->msg_line, 36, good); -test.c:1269: hprint(v->msg_line, 46, bad); -test.c:1270: hprint(v->msg_line, 56, xor); -test.c:1271: dprint(v->msg_line, 66, ecount, 5, 0); -test.c:1272: v->eadr = adr; -test.c:1273: v->exor = xor; -test.c:1283: if (v->printmode == PRINTMODE_NONE) { -test.c:1288: cprint(v->msg_line, 36, corrected?"corrected ":" "); -test.c:1289: cprint(v->msg_line, 46, " "); -test.c:1290: hprint2(v->msg_line, 56, syndrom, 2); -test.c:1291: cprint(v->msg_line, 66, "ECC"); -test.c:1292: dprint(v->msg_line, 71, channel, 2, 0); -test.c:1303: if (v->test == 5) { -test.c:1309: if (v->printmode == PRINTMODE_NONE) { -test.c:1313: cprint(v->msg_line, 36, "Parity error detected "); -test.c:1329: if (v->numpatn == 0) -test.c:1334: cprint (v->msg_line, 0, "badram="); -test.c:1337: for (idx = 0; idx < v->numpatn; idx++) { -test.c:1343: cprint (v->msg_line, x, "0x"); -test.c:1344: hprint (v->msg_line, x+2, v->patn[idx].adr ); -test.c:1345: cprint (v->msg_line, x+10, ",0x"); -test.c:1346: hprint (v->msg_line, x+13, v->patn[idx].mask); -test.c:1347: if (idx+1 < v->numpatn) -test.c:1348: cprint (v->msg_line, x+21, ","); -test.c:1365: v->total_ticks++; -test.c:1370: while (i > v->tptr) { -test.c:1371: if (v->tptr >= BAR_SIZE) { -test.c:1374: cprint(1, COL_MID+9+v->tptr, "#"); -test.c:1375: v->tptr++; -test.c:1378: pct = 100*v->total_ticks/v->pass_ticks; -test.c:1381: while (i > v->pptr) { -test.c:1382: if (v->pptr >= BAR_SIZE) { -test.c:1385: cprint(0, COL_MID+9+v->pptr, "#"); -test.c:1386: v->pptr++; -test.c:1392: if (v->rdtsc) { -test.c:1399: :"g" (v->startl), "g" (v->starth), -test.c:1401: t = h * ((unsigned)0xffffffff / v->clks_msec) / 1000; -test.c:1402: t += (l / v->clks_msec) / 1000; -test.c~:40: p = (ulong *)roundup((ulong)v->map[0].start, 0x1ffff); -test.c~:45: end = v->map[segs-1].end; -test.c~:72: if (v->pmap[v->msegs - 1].end > (0x800000 >> 12)) { -test.c~:81: p = v->map[j].start; -test.c~:84: end = v->map[j].end; -test.c~:136: start = v->map[j].start; -test.c~:137: end = v->map[j].end; -test.c~:180: start = v->map[j].start; -test.c~:181: end = v->map[j].end; -test.c~:257: start = v->map[j].start; -test.c~:258: end = v->map[j].end; -test.c~:298: start = v->map[j].start; -test.c~:299: end = v->map[j].end; -test.c~:364: start = v->map[j].start; -test.c~:365: end = v->map[j].end; -test.c~:448: start = v->map[j].start; -test.c~:449: end = v->map[j].end; -test.c~:516: start = v->map[j].start; -test.c~:517: end = v->map[j].end; -test.c~:623: start = v->map[j].start; -test.c~:624: end = v->map[j].end; -test.c~:735: start = v->map[j].start; -test.c~:736: end = v->map[j].end; -test.c~:779: start = v->map[j].start; -test.c~:780: end = v->map[j].end; -test.c~:838: start = v->map[j].start; -test.c~:839: end = v->map[j].end; -test.c~:916: start = (ulong)v->map[j].start; -test.c~:925: end = (ulong)v->map[j].end; -test.c~:985: start = (ulong)v->map[j].start; -test.c~:994: end = (ulong)v->map[j].end; -test.c~:1052: start = (ulong)v->map[j].start; -test.c~:1061: end = (ulong)v->map[j].end; -test.c~:1139: if (v->printmode == PRINTMODE_ADDRESSES) { -test.c~:1142: if ((ulong)adr == (ulong)v->eadr && xor == v->exor) { -test.c~:1144: dprint(v->msg_line, 62, ++ecount, 5, 0); -test.c~:1149: } else if (v->printmode == PRINTMODE_PATTERNS) { -test.c~:1168: if (v->printmode == PRINTMODE_NONE) { -test.c~:1184: if (v->printmode == PRINTMODE_NONE) { -test.c~:1204: if (v->printmode == PRINTMODE_ADDRESSES) { -test.c~:1206: } else if (v->printmode == PRINTMODE_PATTERNS) { -test.c~:1226: ++(v->ecount); -test.c~:1227: tseq[v->test].errors++; -test.c~:1232: dprint(LINE_INFO, COL_ERR, v->ecount, 6, 0); -test.c~:1248: dprint(v->msg_line, 0, v->test, 3, 0); -test.c~:1249: dprint(v->msg_line, 4, v->pass, 5, 0); -test.c~:1250: hprint(v->msg_line, 11, page); -test.c~:1251: hprint2(v->msg_line, 19, offset, 3); -test.c~:1252: cprint(v->msg_line, 22, " - . MB"); -test.c~:1253: dprint(v->msg_line, 25, mb, 5, 0); -test.c~:1254: dprint(v->msg_line, 31, ((page & 0xF)*10)/16, 1, 0); -test.c~:1268: hprint(v->msg_line, 36, good); -test.c~:1269: hprint(v->msg_line, 46, bad); -test.c~:1270: hprint(v->msg_line, 56, xor); -test.c~:1271: dprint(v->msg_line, 66, ecount, 5, 0); -test.c~:1272: v->eadr = adr; -test.c~:1273: v->exor = xor; -test.c~:1285: if (v->test == 5) { -test.c~:1291: if (v->printmode == PRINTMODE_NONE) { -test.c~:1295: cprint(v->msg_line, 36, "Parity error detected "); -test.c~:1311: if (v->numpatn == 0) -test.c~:1316: cprint (v->msg_line, 0, "badram="); -test.c~:1319: for (idx = 0; idx < v->numpatn; idx++) { -test.c~:1325: cprint (v->msg_line, x, "0x"); -test.c~:1326: hprint (v->msg_line, x+2, v->patn[idx].adr ); -test.c~:1327: cprint (v->msg_line, x+10, ",0x"); -test.c~:1328: hprint (v->msg_line, x+13, v->patn[idx].mask); -test.c~:1329: if (idx+1 < v->numpatn) -test.c~:1330: cprint (v->msg_line, x+21, ","); -test.c~:1347: v->total_ticks++; -test.c~:1352: while (i > v->tptr) { -test.c~:1353: if (v->tptr >= BAR_SIZE) { -test.c~:1356: cprint(1, COL_MID+9+v->tptr, "#"); -test.c~:1357: v->tptr++; -test.c~:1360: pct = 100*v->total_ticks/v->pass_ticks; -test.c~:1363: while (i > v->pptr) { -test.c~:1364: if (v->pptr >= BAR_SIZE) { -test.c~:1367: cprint(0, COL_MID+9+v->pptr, "#"); -test.c~:1368: v->pptr++; -test.c~:1374: if (v->rdtsc) { -test.c~:1381: :"g" (v->startl), "g" (v->starth), -test.c~:1383: t = h * ((unsigned)0xffffffff / v->clks_msec) / 1000; -test.c~:1384: t += (l / v->clks_msec) / 1000; diff --git a/head.S b/head.S index 1d31263..400f183 100644 --- a/head.S +++ b/head.S @@ -8,6 +8,7 @@ * * 1-Jan-96 Modified by Chris Brady for use as a boot/loader for MemTest-86. * Setup the memory management for flat non-paged linear addressing. + * 17 May 2004 : Added X86_PWRCAP for AMD64 (Memtest86+ - Samuel D.) */ .text @@ -27,6 +28,7 @@ #define X86_CAPABILITY 8 #define X86_VENDOR_ID 12 #define X86_CACHE 24 +#define X86_PWRCAP 40 .code32 .globl startup_32 @@ -365,6 +367,9 @@ not_intel: movl $0x80000006,%eax # Use the CPUID instruction to get cache info cpuid movl %ecx,X86_CACHE+8(%esi) + movl $0x80000007,%eax # Use the CPUID instruction to get AMD Powercap + cpuid + movl %edx,X86_PWRCAP(%esi) not_amd: movl X86_VENDOR_ID+8(%esi), %eax diff --git a/init.c b/init.c index cbae911..90b8dec 100644 --- a/init.c +++ b/init.c @@ -51,7 +51,7 @@ static void display_init(void) for(i=0, pp=(char *)(SCREEN_ADR+1); istartl),"=d" (v->starth)); v->snapl = v->startl; v->snaph = v->starth; diff --git a/main.c b/main.c index 37025aa..ffa81b0 100644 --- a/main.c +++ b/main.c @@ -215,7 +215,12 @@ void do_test(void) } break; case 1: /* Extended tests */ - if (v->test <= DEFTESTS) { + if ((v->test <= DEFTESTS) || (v->test > DEFTESTS2)) { + goto skip_test; + } + break; + case 2: /* All tests */ + if (v->test > DEFTESTS2) { goto skip_test; } break; diff --git a/precomp.bin b/precomp.bin index 608ed50..2a600d6 100755 Binary files a/precomp.bin and b/precomp.bin differ diff --git a/test.c b/test.c index 6adc967..03804c6 100644 --- a/test.c +++ b/test.c @@ -1480,9 +1480,10 @@ void do_tick(void) void sleep(int n) { - int i; + int i, ip; ulong sh, sl, l, h, t; - + + ip = 0; /* save the starting time */ asm __volatile__( "rdtsc":"=a" (sl),"=d" (sh)); @@ -1509,6 +1510,12 @@ void sleep(int n) i = t % 60; dprint(LINE_TIME, COL_TIME+9, i%10, 1, 0); dprint(LINE_TIME, COL_TIME+8, i/10, 1, 0); + + if (i != ip) { + check_input(); + ip = i; + } + t /= 60; i = t % 60; dprint(LINE_TIME, COL_TIME+6, i % 10, 1, 0); diff --git a/test.h b/test.h index 42bdef0..b9938a4 100644 --- a/test.h +++ b/test.h @@ -37,6 +37,7 @@ struct mem_info_t { typedef unsigned long ulong; #define SPINSZ 0x800000 #define DEFTESTS 7 +#define DEFTESTS2 11 #define MOD_SZ 20 #define BAILOUT if (bail) goto skip_test; #define BAILR if (bail) return; @@ -235,6 +236,7 @@ struct cpu_ident { long capability; char vend_id[12]; unsigned char cache_info[16]; + long pwrcap; }; #define X86_FEATURE_PAE (0*32+ 6) /* Physical Address Extensions */ -- cgit v1.2.3-55-g7522