From 79de8c96dac6b6d4491c4e6302c4c388c8682867 Mon Sep 17 00:00:00 2001 From: Michael Brown Date: Tue, 4 May 2010 21:03:39 +0100 Subject: [import] Import version 4.10 http://www.memtest.org/download/4.10/memtest86+-4.10.tar.gz --- Makefile | 2 +- README | 2 +- changelog | 26 ++---- controller.c | 272 ++++++++++++++++++++++++++++++++++++++++++++++++++++++- head.S | 49 +++++++++- init.c | 61 +++++++++++-- lib.c | 6 +- makeiso.sh | 6 +- memtest.exe | Bin 161064 -> 0 bytes memtest.lds | 2 +- mt86+_loader | Bin 784 -> 784 bytes mt86+_loader.asm | 4 +- precomp.bin | Bin 160280 -> 165080 bytes test.h | 20 +++- 14 files changed, 406 insertions(+), 44 deletions(-) delete mode 100644 memtest.exe diff --git a/Makefile b/Makefile index 5ae302a..f51b813 100644 --- a/Makefile +++ b/Makefile @@ -11,7 +11,7 @@ FDISK=/dev/fd0 AS=as -32 CC=gcc -CFLAGS= -Wall -march=i486 -m32 -O2 -fomit-frame-pointer -fno-builtin -ffreestanding -fPIC +CFLAGS= -Wall -march=i486 -m32 -O2 -fomit-frame-pointer -fno-builtin -ffreestanding -fPIC -fno-stack-protector OBJS= head.o reloc.o main.o test.o init.o lib.o patn.o screen_buffer.o \ config.o linuxbios.o memsize.o pci.o controller.o random.o spd.o \ diff --git a/README b/README index e02ca58..cbdb42e 100644 --- a/README +++ b/README @@ -1,4 +1,4 @@ -Memtest86++ v4.00 +Memtest86++ v4.10 ==================== Table of Contents diff --git a/changelog b/changelog index 5914646..5ca01c5 100644 --- a/changelog +++ b/changelog @@ -1,19 +1,11 @@ -Memtest86+ V4.00 changelog +Memtest86+ V4.10 changelog -------------------------- - - Major Architectural changes - - First pass twice faster (reduced iterations) - - Detect DDR2/3 brands and part numbers - - Corrected detection for Intel "Lynnfield" CPU - - Added detection for Intel "Clarkdale" CPU - - Added detection for Intel "Gulftown" CPU - - Corrected detection for AMD 45nm K10 CPU - - Added detection for AMD "Magny-Cours" CPU - - Solved crash with AMD Geode LX - - Added detection for Intel XMP Memory - - Added for CPU w/ 0.5/1.5/3/6/12/16/18/24MB L3 - - Added "clean" DMI detection for DDR3/FBDIMM2 - - Better detection of Integrated Memory Ctrl - - Complies with SMBIOS 2.6.1 specs - - Fixed compilation issues with gcc 4.2+ - - Many others bug fixes + - Added support for Core i7 Extreme CPU (32nm) + - Added support for Core i5/i3 (32 nm) + - Added support for Pentium Gxxxx (32 mn) + - Added support for Westmere-based Xeon + - Added preliminary support for Intel Sandy Bridge + - Added support for AMD 6-cores CPU + - Added detection for Intel 3200/3210 + - Many bug fixes diff --git a/controller.c b/controller.c index 948785b..89589ab 100644 --- a/controller.c +++ b/controller.c @@ -16,6 +16,7 @@ #include "spd.h" #include "test.h" + int col, col2; int nhm_bus = 0x3F; @@ -160,6 +161,8 @@ void print_fsb_info(float val, const char *text_fsb, const char *text_ddr) { col2 += 1; } + + static void poll_fsb_nothing(void) { /* Code to run for no specific fsb detection */ @@ -187,6 +190,23 @@ static void poll_nothing(void) return; } +static void setup_wmr(void) +{ + + // Activate MMR I/O + ulong dev0; + ctrl.cap = ECC_CORRECT; + + pci_conf_read( 0, 0, 0, 0x48, 4, &dev0); + if (!(dev0 & 0x1)) { + pci_conf_write( 0, 0, 0, 0x48, 1, dev0 | 1); + } + + ctrl.mode = ECC_NONE; + +} + + static void setup_nhm(void) { static float possible_nhm_bus[] = {0xFF, 0x7F, 0x3F}; @@ -204,7 +224,7 @@ static void setup_nhm(void) pci_conf_read( possible_nhm_bus[i], 3, 4, 0x02, 2, &did); vid &= 0xFFFF; did &= 0xFF00; - if(vid == 0x8086 && did == 0x2C00) { + if(vid == 0x8086 && did >= 0x2C00) { nhm_bus = possible_nhm_bus[i]; } } @@ -223,6 +243,41 @@ static void setup_nhm(void) } +static void setup_nhm32(void) +{ + static float possible_nhm_bus[] = {0xFF, 0x7F, 0x3F}; + unsigned long did, vid, mc_control, mc_ssrcontrol; + int i; + + //Nehalem supports Scrubbing */ + ctrl.cap = ECC_SCRUB; + ctrl.mode = ECC_NONE; + + /* First, locate the PCI bus where the MCH is located */ + + for(i = 0; i < sizeof(possible_nhm_bus); i++) { + pci_conf_read( possible_nhm_bus[i], 3, 4, 0x00, 2, &vid); + pci_conf_read( possible_nhm_bus[i], 3, 4, 0x02, 2, &did); + vid &= 0xFFFF; + did &= 0xFF00; + if(vid == 0x8086 && did >= 0x2C00) { + nhm_bus = possible_nhm_bus[i]; + } +} + + /* Now, we have the last IMC bus number in nhm_bus */ + /* Check for ECC & Scrub */ + pci_conf_read(nhm_bus, 3, 0, 0x48, 2, &mc_control); + if((mc_control >> 1) & 1) { + ctrl.mode = ECC_CORRECT; + pci_conf_read(nhm_bus, 3, 2, 0x48, 2, &mc_ssrcontrol); + if(mc_ssrcontrol & 1) { + ctrl.mode = ECC_SCRUB; + } + } + +} + static void setup_amd64(void) { @@ -1175,6 +1230,58 @@ static float getNHMmultiplier(void) return coef; } + +void getIntelPNS(void) +{ + int i,j; + long psn_eax, psn_ebx, psn_ecx, psn_edx; + long char_hex; + long ocpuid = 0x80000002; + + for(j = 0; j < 4; j++) + { + + asm __volatile__( + "pushl %%ebx\n\t" \ + "cpuid\n\t" \ + "movl %%ebx, %1\n\t" \ + "popl %%ebx\n\t" \ + : "=a" (psn_eax), "=r" (psn_ebx), "=c" (psn_ecx), "=d" (psn_edx) + : "a" (ocpuid) + : "cc" + ); + + + for(i = 0; i < 4; i++) + { + char_hex = (psn_eax >> (i*8)) & 0xff; + cprint(LINE_CPU+5, col + i, convert_hex_to_char(char_hex)); + + char_hex = (psn_ebx >> (i*8)) & 0xff; + cprint(LINE_CPU+5, col + i + 4, convert_hex_to_char(char_hex)); + + if(psn_ecx != 0x20202020) + { + char_hex = (psn_ecx >> (i*8)) & 0xff; + cprint(LINE_CPU+5, col + i + 8, convert_hex_to_char(char_hex)); + + char_hex = (psn_edx >> (i*8)) & 0xff; + cprint(LINE_CPU+5, col + i + 12, convert_hex_to_char(char_hex)); + } + else + { + char_hex = (psn_edx >> (i*8)) & 0xff; + cprint(LINE_CPU+5, col + i + 8, convert_hex_to_char(char_hex)); + } + } + (psn_ecx != 0x20202020)?(col += 16):(col +=12); + if(psn_edx == 0x20202020) { col -= 4; } + ocpuid++; + } + + col -= 16; +} + static void poll_fsb_amd64(void) { unsigned int mcgsrl; @@ -2092,6 +2199,98 @@ static void poll_fsb_nhm(void) { } +static void poll_fsb_nhm32(void) { + + double dramclock, dramratio, fsb; + unsigned long mc_dimm_clk_ratio, qpi_pll_status; + float coef = getNHMmultiplier(); + float qpi_speed; + + fsb = ((extclock /1000) / coef); + + /* Print FSB */ + cprint(LINE_CPU+5, col +1, "/ BCLK : "); + col += 10; + dprint(LINE_CPU+5, col, fsb, 3,0); + col += 3; + cprint(LINE_CPU+5, col +1, "MHz"); + col += 4; + + /* Print QPI Speed (if ECC not supported) */ + if(ctrl.mode == ECC_NONE && cpu_id.model == 12) { + pci_conf_read(nhm_bus, 2, 1, 0x50, 2, &qpi_pll_status); + qpi_speed = (qpi_pll_status & 0x7F) * ((extclock / 1000) / coef) * 2; + cprint(LINE_CPU+5, col +1, "/ QPI : "); + col += 9; + dprint(LINE_CPU+5, col, qpi_speed/1000, 1,0); + col += 1; + cprint(LINE_CPU+5, col, "."); + col += 1; + qpi_speed = ((qpi_speed / 1000) - (int)(qpi_speed / 1000)) * 10; + dprint(LINE_CPU+5, col, qpi_speed, 1,0); + col += 1; + cprint(LINE_CPU+5, col +1, "GT/s"); + col += 5; + } + + /* Get the clock ratio */ + + pci_conf_read(nhm_bus, 3, 4, 0x50, 2, &mc_dimm_clk_ratio); + dramratio = (mc_dimm_clk_ratio & 0x1F); + + // Compute RAM Frequency + fsb = ((extclock / 1000) / coef); + dramclock = fsb * dramratio / 2; + + // Print DRAM Freq + print_fsb_info(dramclock, "RAM : ", "DDR3-"); + +} + +static void poll_fsb_wmr(void) { + + double dramclock, dramratio, fsb; + unsigned long dev0, mchcfg; + float coef = getNHMmultiplier(); + long *ptr; + + fsb = ((extclock / 1000) / coef); + + if(ctrl.mode == ECC_NONE) + { + col = 0; + cprint(LINE_CPU+5, col, "IMC : "); col += 6; + getIntelPNS(); + //cprint(LINE_CPU+5, col, "(ECC : Disabled)"); + //col += 16; + } + + /* Print FSB */ + cprint(LINE_CPU+5, col +1, "/ BCLK : "); + col += 10; + dprint(LINE_CPU+5, col, fsb, 3,0); + col += 3; + cprint(LINE_CPU+5, col +1, "MHz"); + col += 4; + + /* Find dramratio */ + pci_conf_read( 0, 0, 0, 0x48, 4, &dev0); + dev0 &= 0xFFFFC000; + ptr=(long*)(dev0+0x2C20); + mchcfg = *ptr & 0xFFFF; + dramratio = 1; + + /* Get the clock ratio */ + dramratio = 0.25 * (float)(*ptr & 0x1F); + + // Compute RAM Frequency + dramclock = fsb * dramratio; + + // Print DRAM Freq + print_fsb_info(dramclock, "RAM : ", "DDR3-"); + +} + /* ------------------ Here the code for Timings detection ------------------ */ /* ------------------------------------------------------------------------- */ @@ -2484,6 +2683,71 @@ static void poll_timings_p35(void) { } +static void poll_timings_wmr(void) { + + float cas; + int rcd, rp, ras; + ulong dev0, c0ckectrl, c1ckectrl, offset; + ulong ODT_Control_Register, Precharge_Register, ACT_Register, Read_Register, MRC_Register; + long *ptr; + + //Now, read MMR Base Address + pci_conf_read( 0, 0, 0, 0x48, 4, &dev0); + dev0 &= 0xFFFFC000; + + ptr = (long*)(dev0+0x260); + c0ckectrl = *ptr & 0xFFFFFFFF; + + ptr = (long*)(dev0+0x660); + c1ckectrl = *ptr & 0xFFFFFFFF; + + // If DIMM 0 not populated, check DIMM 1 + ((c0ckectrl) >> 20 & 0xF)?(offset = 0):(offset = 0x400); + + ptr = (long*)(dev0+offset+0x265); + ODT_Control_Register = *ptr & 0xFFFFFFFF; + + ptr = (long*)(dev0+offset+0x25D); + Precharge_Register = *ptr & 0xFFFFFFFF; + + ptr = (long*)(dev0+offset+0x252); + ACT_Register = *ptr & 0xFFFFFFFF; + + ptr = (long*)(dev0+offset+0x258); + Read_Register = *ptr & 0xFFFFFFFF; + + ptr = (long*)(dev0+offset+0x240); + MRC_Register = *ptr & 0xFFFFFFFF; + + // CAS Latency (tCAS) + if(MRC_Register & 0xF) { + cas = (MRC_Register & 0xF) + 3.0f; + } else { + cas = ((ODT_Control_Register >> 8)& 0x3F) - 5.0f; + } + + // RAS-To-CAS (tRCD) + rcd = (Read_Register >> 17) & 0xF; + + // RAS Precharge (tRP) + rp = (ACT_Register >> 13) & 0xF; + + // RAS Active to precharge (tRAS) + ras = Precharge_Register & 0x3F; + + print_timings_info(cas, rcd, rp, ras); + + cprint(LINE_CPU+6, col2+1, "/"); col2 +=2; + + if ((c0ckectrl >> 20 & 0xF) && (c1ckectrl >> 20 & 0xF)) { + cprint(LINE_CPU+6, col2+1, "Dual Channel"); + } else { + cprint(LINE_CPU+6, col2+1, "Single Channel"); + } + +} + + static void poll_timings_5400(void) { // Thanks for CDH optis @@ -2938,7 +3202,7 @@ static void poll_timings_nhm(void) { fvc_bn = 4; } else if(mc_control & 2) { fvc_bn = 5; - } else if(mc_control & 7) { + } else if(mc_control & 4) { fvc_bn = 6; } @@ -3098,6 +3362,7 @@ static struct pci_memory_controller controllers[] = { { 0x8086, 0x29C0, "Intel P35/G33", 0, poll_fsb_i965, poll_timings_p35, setup_p35, poll_nothing}, { 0x8086, 0x29D0, "Intel Q33", 0, poll_fsb_i965, poll_timings_p35, setup_p35, poll_nothing}, { 0x8086, 0x29E0, "Intel X38/X48", 0, poll_fsb_i965, poll_timings_p35, setup_p35, poll_nothing}, + { 0x8086, 0x29F0, "Intel 3200/3210", 0, poll_fsb_i965, poll_timings_p35, setup_p35, poll_nothing}, { 0x8086, 0x2E10, "Intel Q45/Q43", 0, poll_fsb_i965, poll_timings_p35, setup_p35, poll_nothing}, { 0x8086, 0x2E20, "Intel P45/G45", 0, poll_fsb_i965, poll_timings_p35, setup_p35, poll_nothing}, { 0x8086, 0x2E30, "Intel G41", 0, poll_fsb_i965, poll_timings_p35, setup_p35, poll_nothing}, @@ -3113,7 +3378,8 @@ static struct pci_memory_controller controllers[] = { /* Integrated Memory Controllers */ { 0xFFFF, 0x0001, "Core IMC", 0, poll_fsb_nhm, poll_timings_nhm, setup_nhm, poll_nothing}, - { 0xFFFF, 0x0002, "Core IMC2", 0, poll_fsb_nhm, poll_timings_nothing, setup_nhm, poll_nothing}, + { 0xFFFF, 0x0002, "Core IMC 32nm", 0, poll_fsb_nhm32, poll_timings_nhm, setup_nhm32, poll_nothing}, + { 0xFFFF, 0x0003, "Core IMC 32nm", 0, poll_fsb_wmr, poll_timings_wmr, setup_wmr, poll_nothing}, { 0xFFFF, 0x0100, "AMD K8 IMC", 0, poll_fsb_amd64, poll_timings_amd64, setup_amd64, poll_amd64 }, { 0xFFFF, 0x0101, "AMD K10 IMC", 0, poll_fsb_k10, poll_timings_k10, setup_k10, poll_nothing } diff --git a/head.S b/head.S index a5590be..4a5c872 100644 --- a/head.S +++ b/head.S @@ -31,6 +31,22 @@ #define X86_PWRCAP 40 #define X86_EXT 44 #define X86_FFL 48 +#define X86_DCACHE0_EAX 52 +#define X86_DCACHE0_EBX 56 +#define X86_DCACHE0_ECX 60 +#define X86_DCACHE0_EDX 64 +#define X86_DCACHE1_EAX 68 +#define X86_DCACHE1_EBX 72 +#define X86_DCACHE1_ECX 76 +#define X86_DCACHE1_EDX 80 +#define X86_DCACHE2_EAX 84 +#define X86_DCACHE2_EBX 88 +#define X86_DCACHE2_ECX 92 +#define X86_DCACHE2_EDX 96 +#define X86_DCACHE3_EAX 100 +#define X86_DCACHE3_EBX 104 +#define X86_DCACHE3_ECX 108 +#define X86_DCACHE3_EDX 112 .code32 .globl startup_32 @@ -373,6 +389,37 @@ have_cpuid: movl %ebx, X86_CACHE+4(%esi) movl %ecx, X86_CACHE+8(%esi) movl %edx, X86_CACHE+12(%esi) +# Grab deterministic cache information (for 32nm Intel CPU) + cmpw $0x0000,%dx + jne id_done + movl $4, %eax + movl $0, %ecx + cpuid + movl %eax, X86_DCACHE0_EAX(%esi) + movl %ebx, X86_DCACHE0_EBX(%esi) + movl %ecx, X86_DCACHE0_ECX(%esi) + movl %edx, X86_DCACHE0_EDX(%esi) + movl $4, %eax + movl $1, %ecx + cpuid + movl %eax, X86_DCACHE1_EAX(%esi) + movl %ebx, X86_DCACHE1_EBX(%esi) + movl %ecx, X86_DCACHE1_ECX(%esi) + movl %edx, X86_DCACHE1_EDX(%esi) + movl $4, %eax + movl $2, %ecx + cpuid + movl %eax, X86_DCACHE2_EAX(%esi) + movl %ebx, X86_DCACHE2_EBX(%esi) + movl %ecx, X86_DCACHE2_ECX(%esi) + movl %edx, X86_DCACHE2_EDX(%esi) + movl $4, %eax + movl $3, %ecx + cpuid + movl %eax, X86_DCACHE3_EAX(%esi) + movl %ebx, X86_DCACHE3_EBX(%esi) + movl %ecx, X86_DCACHE3_ECX(%esi) + movl %edx, X86_DCACHE3_EDX(%esi) jmp id_done not_intel: @@ -980,6 +1027,6 @@ mem_info: .bss .balign 16 stack: - . = . + 4096 + . = . + 8192 stack_top: .previous diff --git a/init.c b/init.c index 4b3248a..d965ec3 100644 --- a/init.c +++ b/init.c @@ -3,7 +3,7 @@ * Released under version 2 of the Gnu Public License. * By Chris Brady, cbrady@sgi.com * ---------------------------------------------------- - * MemTest86+ V4.00 Specific code (GPL V2.0) + * MemTest86+ V4.10 Specific code (GPL V2.0) * By Samuel DEMEULEMEESTER, sdemeule@memtest.org * http://www.canardpc.com - http://www.memtest.org */ @@ -65,7 +65,7 @@ static void display_init(void) for(i=0, pp=(char *)(SCREEN_ADR+1); i> 5) & 7) == 1) + { + + long dcache[] = { cpu_id.dcache0_eax, cpu_id.dcache0_ebx, cpu_id.dcache0_ecx, cpu_id.dcache0_edx, + cpu_id.dcache1_eax, cpu_id.dcache1_ebx, cpu_id.dcache1_ecx, cpu_id.dcache1_edx, + cpu_id.dcache2_eax, cpu_id.dcache2_ebx, cpu_id.dcache2_ecx, cpu_id.dcache2_edx, + cpu_id.dcache3_eax, cpu_id.dcache3_ebx, cpu_id.dcache3_ecx, cpu_id.dcache3_edx + }; + + for(i=0; i<4; i++) + { + switch((dcache[i*4] >> 5) & 7) + { + case 1: + // We don't want L1 I-Cache, only L1 D-Cache + if((dcache[i*4] & 3) != 2) + { + l1_cache = (((dcache[i*4+1] >> 22) & 0x3FF) + 1) * (((dcache[i*4+1] >> 12) & 0x3FF) + 1); + l1_cache *= ((dcache[i*4+1] & 0xFFF) + 1) * (dcache[i*4+2] + 1) / 1024; + } + break; + case 2: + l2_cache = (((dcache[i*4+1] >> 22) & 0x3FF) + 1) * (((dcache[i*4+1] >> 12) & 0x3FF) + 1); + l2_cache *= ((dcache[i*4+1] & 0xFFF) + 1) * (dcache[i*4+2] + 1) / 1024; + break; + case 3: + l3_cache = (((dcache[i*4+1] >> 22) & 0x3FF) + 1) * (((dcache[i*4+1] >> 12) & 0x3FF) + 1); + l3_cache *= ((dcache[i*4+1] & 0xFFF) + 1) * (dcache[i*4+2] + 1) / 1024; + break; + } + } + } + switch(cpu_id.type) { case 5: @@ -818,7 +853,7 @@ void cpu_type(void) if(((cpu_id.ext >> 16) & 0xF) > 1) { cprint(LINE_CPU, 0, "Intel Core i3/i5"); tsc_invariable = 1; - imc_type = 0x0002; + imc_type = 0x0003; off = 16; } else { cprint(LINE_CPU, 0, "Intel EP80579"); @@ -876,10 +911,16 @@ void cpu_type(void) break; case 10: if (((cpu_id.ext >> 16) & 0xF) != 0) { - tsc_invariable = 1; - imc_type = 0x0001; - cprint(LINE_CPU, 0, "Intel Core i7"); - off = 13; + tsc_invariable = 1; + if(((cpu_id.ext >> 16) & 0xF) > 1) { + cprint(LINE_CPU, 0, "Intel SNB"); + imc_type = 0x0003; + off = 9; + } else { + imc_type = 0x0001; + cprint(LINE_CPU, 0, "Intel Core i7"); + off = 13; + } } else { cprint(LINE_CPU, 0, "Pentium III Xeon"); off = 16; @@ -887,10 +928,10 @@ void cpu_type(void) break; case 12: if (((cpu_id.ext >> 16) & 0xF) > 1) { - cprint(LINE_CPU, 0, "Intel Core i9"); + cprint(LINE_CPU, 0, "Core i7 (32nm)"); tsc_invariable = 1; imc_type = 0x0002; - off = 13; + off = 14; } else { l1_cache = 24; cprint(LINE_CPU, 0, "Atom (0.045)"); @@ -1369,7 +1410,7 @@ ulong memspeed(ulong src, ulong len, int iter, int type) "lodsl\n\t" \ "loop L2\n\t" \ :: "g" (src), "g" (wlen) - : "esi", "ecx" + : "esi", "ecx", "eax" ); } asm __volatile__ ("rdtsc":"=a" (end_low),"=d" (end_high)); diff --git a/lib.c b/lib.c index 27c7ec0..d107039 100644 --- a/lib.c +++ b/lib.c @@ -24,7 +24,7 @@ short serial_cons = SERIAL_CONSOLE_DEFAULT; #error Bad SERIAL_TTY. Only ttyS0 and ttyS1 are supported. #endif short serial_tty = SERIAL_TTY; -const short serial_base_ports[] = {0x3f8, 0x2f8}; +const short serial_base_ports[] = {0x3f8, 0x2f8, 0x3e8, 0x2e8}; #if ((115200%SERIAL_BAUD_RATE) != 0) #error Bad default baud rate @@ -1053,8 +1053,8 @@ void serial_console_setup(char *param) if (option == param) return; /* there were no digits */ - if (tty > 1) - return; /* only ttyS0 and ttyS1 supported */ + if (tty > 3) + return; /* only ttyS0 to ttyS3 supported */ if (*option == '\0' || *option == ' ') goto save_tty; /* no options given, just ttyS? */ diff --git a/makeiso.sh b/makeiso.sh index 95751b5..bc1c137 100755 --- a/makeiso.sh +++ b/makeiso.sh @@ -37,9 +37,9 @@ cd cd echo -e "There is nothing to do here\r\r\nMemtest86+ is located on the bootsector of this CD\r\r\n" > README.TXT echo -e "Just boot from this CD and Memtest86+ will launch" >> README.TXT -mkisofs -A "MKISOFS 1.1.2" -p "Memtest86+ 4.00" -publisher "Samuel D. " -b boot/memtest.img -c boot/boot.catalog -V "MT201" -o memtest.iso . -mv memtest.iso ../mt400.iso +mkisofs -A "MKISOFS 1.1.2" -p "Memtest86+ 4.10" -publisher "Samuel D. " -b boot/memtest.img -c boot/boot.catalog -V "MT410" -o memtest.iso . +mv memtest.iso ../mt410.iso cd .. rm -rf cd -echo "Done! Memtest86+ 4.00 ISO is mt400.iso" +echo "Done! Memtest86+ 4.10 ISO is mt410.iso" diff --git a/memtest.exe b/memtest.exe deleted file mode 100644 index a79b407..0000000 Binary files a/memtest.exe and /dev/null differ diff --git a/memtest.lds b/memtest.lds index 1d661b3..2906a24 100644 --- a/memtest.lds +++ b/memtest.lds @@ -3,7 +3,7 @@ OUTPUT_ARCH(i386); ENTRY(_start); SECTIONS { - . = 0x10000; + . = 0x5000; _start = . ; .data : { *(.data) diff --git a/mt86+_loader b/mt86+_loader index adac56e..df62b62 100644 Binary files a/mt86+_loader and b/mt86+_loader differ diff --git a/mt86+_loader.asm b/mt86+_loader.asm index 03cea01..a305400 100644 --- a/mt86+_loader.asm +++ b/mt86+_loader.asm @@ -12,8 +12,8 @@ ; The good thing is that you get a single file which can be ; compressed, for example with http://upx.sf.net/ (UPX). -%define fullsize (160280 + buffer - exeh) - ; 160280 is the size of memtest86+ V4.00, adjust as needed! +%define fullsize (165080 + buffer - exeh) + ; 165080 is the size of memtest86+ V4.00, adjust as needed! %define stacksize 2048 %define stackpara ((stacksize + 15) / 16) diff --git a/precomp.bin b/precomp.bin index 6603191..e54513b 100755 Binary files a/precomp.bin and b/precomp.bin differ diff --git a/test.h b/test.h index cfc6fa0..294c297 100644 --- a/test.h +++ b/test.h @@ -14,9 +14,9 @@ #define E801 0x04 #define E820NR 0x08 /* # entries in E820MAP */ #define E820MAP 0x0c /* our map */ -#define E820MAX 32 /* number of entries in E820MAP */ +#define E820MAX 64 /* number of entries in E820MAP */ #define E820ENTRY_SIZE 20 -#define MEMINFO_SIZE 0x28c +#define MEMINFO_SIZE (E820MAP + E820MAX * E820ENTRY_SIZE) #define MAX_DMI_MEMDEVS 16 #ifndef __ASSEMBLY__ @@ -269,6 +269,22 @@ struct cpu_ident { long pwrcap; long ext; long feature_flag; + long dcache0_eax; + long dcache0_ebx; + long dcache0_ecx; + long dcache0_edx; + long dcache1_eax; + long dcache1_ebx; + long dcache1_ecx; + long dcache1_edx; + long dcache2_eax; + long dcache2_ebx; + long dcache2_ecx; + long dcache2_edx; + long dcache3_eax; + long dcache3_ebx; + long dcache3_ecx; + long dcache3_edx; }; struct xadr { -- cgit v1.2.3-55-g7522