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author | Linus Torvalds | 2013-04-02 00:06:34 +0200 |
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committer | Linus Torvalds | 2013-04-02 00:06:34 +0200 |
commit | aae92db9f0f67559198f6ecde922f15e2aeea7e0 (patch) | |
tree | ba3fea6f911409367dc6ba1ad4339f69de4f160d | |
parent | Merge tag 'for-3.9-rc' of git://git.kernel.org/pub/scm/linux/kernel/git/rwlov... (diff) | |
parent | clk: tegra: Allow PLLE training to succeed (diff) | |
download | kernel-qcow2-linux-aae92db9f0f67559198f6ecde922f15e2aeea7e0.tar.gz kernel-qcow2-linux-aae92db9f0f67559198f6ecde922f15e2aeea7e0.tar.xz kernel-qcow2-linux-aae92db9f0f67559198f6ecde922f15e2aeea7e0.zip |
Merge tag 'clk-fixes-for-linus' of git://git.linaro.org/people/mturquette/linux
Pull tegra clock driver fix from Mike Turquette:
"Missing base address in Tegra clock driver results in non-operational
PCIe. On some devices this means that Ethernet will go uninitialized
and other devices will fail. This pull request fixes it with a single
patch to pass the proper base address in the Tegra clock driver."
* tag 'clk-fixes-for-linus' of git://git.linaro.org/people/mturquette/linux:
clk: tegra: Allow PLLE training to succeed
-rw-r--r-- | drivers/clk/tegra/clk-tegra20.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c index 1e2de7305362..f873dcefe0de 100644 --- a/drivers/clk/tegra/clk-tegra20.c +++ b/drivers/clk/tegra/clk-tegra20.c @@ -703,7 +703,7 @@ static void tegra20_pll_init(void) clks[pll_a_out0] = clk; /* PLLE */ - clk = tegra_clk_register_plle("pll_e", "pll_ref", clk_base, NULL, + clk = tegra_clk_register_plle("pll_e", "pll_ref", clk_base, pmc_base, 0, 100000000, &pll_e_params, 0, pll_e_freq_table, NULL); clk_register_clkdev(clk, "pll_e", NULL); |