diff options
| author | Dinh Nguyen | 2019-08-14 17:30:14 +0200 |
|---|---|---|
| committer | Stephen Boyd | 2019-08-14 18:23:21 +0200 |
| commit | c7ec75ea4d5316518adc87224e3cff47192579e7 (patch) | |
| tree | cf349df383621c280409c7788127b939ea6b90d8 | |
| parent | clk: samsung: exynos542x: Move MSCL subsystem clocks to its sub-CMU (diff) | |
| download | kernel-qcow2-linux-c7ec75ea4d5316518adc87224e3cff47192579e7.tar.gz kernel-qcow2-linux-c7ec75ea4d5316518adc87224e3cff47192579e7.tar.xz kernel-qcow2-linux-c7ec75ea4d5316518adc87224e3cff47192579e7.zip | |
clk: socfpga: stratix10: fix rate caclulationg for cnt_clks
Checking bypass_reg is incorrect for calculating the cnt_clk rates.
Instead we should be checking that there is a proper hardware register
that holds the clock divider.
Cc: stable@vger.kernel.org
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
Link: https://lkml.kernel.org/r/20190814153014.12962-1-dinguyen@kernel.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| -rw-r--r-- | drivers/clk/socfpga/clk-periph-s10.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/clk/socfpga/clk-periph-s10.c b/drivers/clk/socfpga/clk-periph-s10.c index 5c50e723ecae..1a191eeeebba 100644 --- a/drivers/clk/socfpga/clk-periph-s10.c +++ b/drivers/clk/socfpga/clk-periph-s10.c @@ -38,7 +38,7 @@ static unsigned long clk_peri_cnt_clk_recalc_rate(struct clk_hw *hwclk, if (socfpgaclk->fixed_div) { div = socfpgaclk->fixed_div; } else { - if (!socfpgaclk->bypass_reg) + if (socfpgaclk->hw.reg) div = ((readl(socfpgaclk->hw.reg) & 0x7ff) + 1); } |