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| author | Kang Luwei | 2018-06-30 02:53:22 +0200 |
|---|---|---|
| committer | Greg Kroah-Hartman | 2018-07-15 13:55:46 +0200 |
| commit | 0a27ff24d59662b1ca8b3f7721a965918f115074 (patch) | |
| tree | 0a0bbd2c4deec56400aabb84f146c738de175e85 /Documentation/ABI | |
| parent | fpga: dfl: add FPGA Management Engine driver basic framework (diff) | |
| download | kernel-qcow2-linux-0a27ff24d59662b1ca8b3f7721a965918f115074.tar.gz kernel-qcow2-linux-0a27ff24d59662b1ca8b3f7721a965918f115074.tar.xz kernel-qcow2-linux-0a27ff24d59662b1ca8b3f7721a965918f115074.zip | |
fpga: dfl: fme: add header sub feature support
The Header Register set is always present for FPGA Management Engine (FME),
this patch implements init and uinit function for header sub feature and
introduces several read-only sysfs interfaces for the capability and
status.
Sysfs interfaces:
* /sys/class/fpga_region/<regionX>/<dfl-fme.x>/ports_num
Read-only. Number of ports implemented
* /sys/class/fpga_region/<regionX>/<dfl-fme.x>/bitstream_id
Read-only. Bitstream (static FPGA region) identifier number. It contains
the detailed version and other information of this static FPGA region.
* /sys/class/fpga_region/<regionX>/<dfl-fme.x>/bitstream_metadata
Read-only. Bitstream (static FPGA region) meta data. It contains the
synthesis date, seed and other information of this static FPGA region.
Signed-off-by: Tim Whisonant <tim.whisonant@intel.com>
Signed-off-by: Enno Luebbers <enno.luebbers@intel.com>
Signed-off-by: Shiva Rao <shiva.rao@intel.com>
Signed-off-by: Christopher Rauer <christopher.rauer@intel.com>
Signed-off-by: Kang Luwei <luwei.kang@intel.com>
Signed-off-by: Xiao Guangrong <guangrong.xiao@linux.intel.com>
Signed-off-by: Wu Hao <hao.wu@intel.com>
Acked-by: Alan Tull <atull@kernel.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'Documentation/ABI')
| -rw-r--r-- | Documentation/ABI/testing/sysfs-platform-dfl-fme | 23 |
1 files changed, 23 insertions, 0 deletions
diff --git a/Documentation/ABI/testing/sysfs-platform-dfl-fme b/Documentation/ABI/testing/sysfs-platform-dfl-fme new file mode 100644 index 000000000000..8fa4febfa4b2 --- /dev/null +++ b/Documentation/ABI/testing/sysfs-platform-dfl-fme @@ -0,0 +1,23 @@ +What: /sys/bus/platform/devices/dfl-fme.0/ports_num +Date: June 2018 +KernelVersion: 4.19 +Contact: Wu Hao <hao.wu@intel.com> +Description: Read-only. One DFL FPGA device may have more than 1 + port/Accelerator Function Unit (AFU). It returns the + number of ports on the FPGA device when read it. + +What: /sys/bus/platform/devices/dfl-fme.0/bitstream_id +Date: June 2018 +KernelVersion: 4.19 +Contact: Wu Hao <hao.wu@intel.com> +Description: Read-only. It returns Bitstream (static FPGA region) + identifier number, which includes the detailed version + and other information of this static FPGA region. + +What: /sys/bus/platform/devices/dfl-fme.0/bitstream_metadata +Date: June 2018 +KernelVersion: 4.19 +Contact: Wu Hao <hao.wu@intel.com> +Description: Read-only. It returns Bitstream (static FPGA region) meta + data, which includes the synthesis date, seed and other + information of this static FPGA region. |