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| author | Chris Zankel | 2014-01-29 07:09:51 +0100 |
|---|---|---|
| committer | Chris Zankel | 2014-01-29 22:47:26 +0100 |
| commit | c0e50d41126e4786d9cf1105bdf783e55c99f915 (patch) | |
| tree | a4b3b7cfe0e0d8fe23008b5c44a5d4ff43081738 /Documentation/devicetree/bindings/rtc/nvidia,tegra20-rtc.txt | |
| parent | xtensa: fix fast_syscall_spill_registers (diff) | |
| download | kernel-qcow2-linux-c0e50d41126e4786d9cf1105bdf783e55c99f915.tar.gz kernel-qcow2-linux-c0e50d41126e4786d9cf1105bdf783e55c99f915.tar.xz kernel-qcow2-linux-c0e50d41126e4786d9cf1105bdf783e55c99f915.zip | |
xtensa: fix fast_syscall_spill_registers
The original implementation could clobber registers under certain conditions.
The Xtensa processor architecture uses windowed registers and the original
implementation was using a4 as a temporary register, which under certain
conditions could be register a0 of the oldest window frame, and didn't always
restore the content correctly.
By moving the _spill_registers routine inside the fast system call, it frees
up one more register (the return address is not required anymore) for the
spill routine.
Signed-off-by: Chris Zankel <chris@zankel.net>
Diffstat (limited to 'Documentation/devicetree/bindings/rtc/nvidia,tegra20-rtc.txt')
0 files changed, 0 insertions, 0 deletions