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| author | Sebastian Hesselbarth | 2013-06-11 08:38:50 +0200 |
|---|---|---|
| committer | Daniel Lezcano | 2013-07-02 15:01:45 +0200 |
| commit | 0c1dcfd53b1066c411d3885cf8156abf59694360 (patch) | |
| tree | bb13bb0c0a6163798cced0045c71d4b02a3a3d11 /Documentation/devicetree | |
| parent | tick: Sanitize broadcast control logic (diff) | |
| download | kernel-qcow2-linux-0c1dcfd53b1066c411d3885cf8156abf59694360.tar.gz kernel-qcow2-linux-0c1dcfd53b1066c411d3885cf8156abf59694360.tar.xz kernel-qcow2-linux-0c1dcfd53b1066c411d3885cf8156abf59694360.zip | |
clocksource: Add Marvell Orion SoC timer
This patch add a DT enabled driver for timers found on Marvell Orion SoCs
(Kirkwood, Dove, Orion5x, and Discovery Innovation). It installs a free-
running clocksource on timer0 and a clockevent source on timer1.
Corresponding device tree documentation is also added.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Tested-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Tested-by: Andrew Lunn <andrew@lunn.ch>
Diffstat (limited to 'Documentation/devicetree')
| -rw-r--r-- | Documentation/devicetree/bindings/timer/marvell,orion-timer.txt | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/timer/marvell,orion-timer.txt b/Documentation/devicetree/bindings/timer/marvell,orion-timer.txt new file mode 100644 index 000000000000..62bb8260cf6a --- /dev/null +++ b/Documentation/devicetree/bindings/timer/marvell,orion-timer.txt @@ -0,0 +1,17 @@ +Marvell Orion SoC timer + +Required properties: +- compatible: shall be "marvell,orion-timer" +- reg: base address of the timer register starting with TIMERS CONTROL register +- interrupt-parent: phandle of the bridge interrupt controller +- interrupts: should contain the interrupts for Timer0 and Timer1 +- clocks: phandle of timer reference clock (tclk) + +Example: + timer: timer { + compatible = "marvell,orion-timer"; + reg = <0x20300 0x20>; + interrupt-parent = <&bridge_intc>; + interrupts = <1>, <2>; + clocks = <&core_clk 0>; + }; |