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| author | Neil Horman | 2013-02-04 20:54:10 +0100 |
|---|---|---|
| committer | Wolfram Sang | 2013-02-10 19:55:25 +0100 |
| commit | 13f35ac14cd0a9a1c4f0034c4c40d0ae98844ce9 (patch) | |
| tree | 18b98cd3edcbb66466e765fbb898640687fb4e52 /Documentation/i2c | |
| parent | i2c: sh_mobile: don't send a stop condition by default inside transfers (diff) | |
| download | kernel-qcow2-linux-13f35ac14cd0a9a1c4f0034c4c40d0ae98844ce9.tar.gz kernel-qcow2-linux-13f35ac14cd0a9a1c4f0034c4c40d0ae98844ce9.tar.xz kernel-qcow2-linux-13f35ac14cd0a9a1c4f0034c4c40d0ae98844ce9.zip | |
i2c: Adding support for Intel iSMT SMBus 2.0 host controller
The iSMT (Intel SMBus Message Transport) supports multi-master I2C/SMBus,
as well as IPMI. It's operation is DMA-based and utilizes descriptors to
initiate transactions on the bus.
The iSMT hardware can act as both a master and a target, although this
driver only supports being a master.
Signed-off-by: Neil Horman <nhorman@tuxdriver.com>
Signed-off-by: Bill Brown <bill.e.brown@intel.com>
Tested-by: Seth Heasley <seth.heasley@intel.com>
Reviewed-by: Jean Delvare <khali@linux-fr.org>
Signed-off-by: Wolfram Sang <wolfram@the-dreams.de>
Diffstat (limited to 'Documentation/i2c')
| -rw-r--r-- | Documentation/i2c/busses/i2c-ismt | 36 |
1 files changed, 36 insertions, 0 deletions
diff --git a/Documentation/i2c/busses/i2c-ismt b/Documentation/i2c/busses/i2c-ismt new file mode 100644 index 000000000000..737355822c0b --- /dev/null +++ b/Documentation/i2c/busses/i2c-ismt @@ -0,0 +1,36 @@ +Kernel driver i2c-ismt + +Supported adapters: + * Intel S12xx series SOCs + +Authors: + Bill Brown <bill.e.brown@intel.com> + + +Module Parameters +----------------- + +* bus_speed (unsigned int) +Allows changing of the bus speed. Normally, the bus speed is set by the BIOS +and never needs to be changed. However, some SMBus analyzers are too slow for +monitoring the bus during debug, thus the need for this module parameter. +Specify the bus speed in kHz. +Available bus frequency settings: + 0 no change + 80 kHz + 100 kHz + 400 kHz + 1000 kHz + + +Description +----------- + +The S12xx series of SOCs have a pair of integrated SMBus 2.0 controllers +targeted primarily at the microserver and storage markets. + +The S12xx series contain a pair of PCI functions. An output of lspci will show +something similar to the following: + + 00:13.0 System peripheral: Intel Corporation Centerton SMBus 2.0 Controller 0 + 00:13.1 System peripheral: Intel Corporation Centerton SMBus 2.0 Controller 1 |