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| author | Mauro Carvalho Chehab | 2019-04-18 22:35:40 +0200 |
|---|---|---|
| committer | Mauro Carvalho Chehab | 2019-07-15 14:20:26 +0200 |
| commit | 6baec31591cee0f2f6d446abb81c828499a6ed23 (patch) | |
| tree | 88060af2f686655c8b1fa8febb7a21662cbaa979 /Documentation/perf/qcom_l3_pmu.rst | |
| parent | docs: blockdev: convert to ReST (diff) | |
| download | kernel-qcow2-linux-6baec31591cee0f2f6d446abb81c828499a6ed23.tar.gz kernel-qcow2-linux-6baec31591cee0f2f6d446abb81c828499a6ed23.tar.xz kernel-qcow2-linux-6baec31591cee0f2f6d446abb81c828499a6ed23.zip | |
docs: perf: convert to ReST
Rename the perf documentation files to ReST, add an
index for them and adjust in order to produce a nice html
output via the Sphinx build system.
At its new index.rst, let's add a :orphan: while this is not linked to
the main index.rst file, in order to avoid build warnings.
Signed-off-by: Mauro Carvalho Chehab <mchehab+samsung@kernel.org>
Diffstat (limited to 'Documentation/perf/qcom_l3_pmu.rst')
| -rw-r--r-- | Documentation/perf/qcom_l3_pmu.rst | 26 |
1 files changed, 26 insertions, 0 deletions
diff --git a/Documentation/perf/qcom_l3_pmu.rst b/Documentation/perf/qcom_l3_pmu.rst new file mode 100644 index 000000000000..a3d014a46bfd --- /dev/null +++ b/Documentation/perf/qcom_l3_pmu.rst @@ -0,0 +1,26 @@ +=========================================================================== +Qualcomm Datacenter Technologies L3 Cache Performance Monitoring Unit (PMU) +=========================================================================== + +This driver supports the L3 cache PMUs found in Qualcomm Datacenter Technologies +Centriq SoCs. The L3 cache on these SOCs is composed of multiple slices, shared +by all cores within a socket. Each slice is exposed as a separate uncore perf +PMU with device name l3cache_<socket>_<instance>. User space is responsible +for aggregating across slices. + +The driver provides a description of its available events and configuration +options in sysfs, see /sys/devices/l3cache*. Given that these are uncore PMUs +the driver also exposes a "cpumask" sysfs attribute which contains a mask +consisting of one CPU per socket which will be used to handle all the PMU +events on that socket. + +The hardware implements 32bit event counters and has a flat 8bit event space +exposed via the "event" format attribute. In addition to the 32bit physical +counters the driver supports virtual 64bit hardware counters by using hardware +counter chaining. This feature is exposed via the "lc" (long counter) format +flag. E.g.:: + + perf stat -e l3cache_0_0/read-miss,lc/ + +Given that these are uncore PMUs the driver does not support sampling, therefore +"perf record" will not work. Per-task perf sessions are not supported. |