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authorGeert Uytterhoeven2017-08-18 11:11:38 +0200
committerSimon Horman2017-09-18 08:05:10 +0200
commit58d6c357b1f7851d632bb70de3a9ada219f201c2 (patch)
tree2c1dbb63d3260382a58fa0949910bb647eba17b4 /arch/arm/boot/dts/r8a7794-silk.dts
parentARM: dts: r8a7793: Convert to new CPG/MSSR bindings (diff)
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ARM: dts: r8a7794: Convert to new CPG/MSSR bindings
Convert the R-Car E2 SoC from the old "Renesas R-Car Gen2 Clock Pulse Generator (CPG)", "Renesas CPG DIV6 Clock", and "Renesas CPG Module Stop (MSTP) Clocks" DT bindings to the new unified "Renesas Clock Pulse Generator / Module Standby and Software Reset" DT bindings. This simplifies the DTS files, and allows to add support for reset control later. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Diffstat (limited to 'arch/arm/boot/dts/r8a7794-silk.dts')
-rw-r--r--arch/arm/boot/dts/r8a7794-silk.dts3
1 files changed, 1 insertions, 2 deletions
diff --git a/arch/arm/boot/dts/r8a7794-silk.dts b/arch/arm/boot/dts/r8a7794-silk.dts
index 4cb5278d104d..edfad0e5ac53 100644
--- a/arch/arm/boot/dts/r8a7794-silk.dts
+++ b/arch/arm/boot/dts/r8a7794-silk.dts
@@ -423,8 +423,7 @@
pinctrl-names = "default";
status = "okay";
- clocks = <&mstp7_clks R8A7794_CLK_DU0>,
- <&mstp7_clks R8A7794_CLK_DU1>,
+ clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>,
<&x2_clk>, <&x3_clk>;
clock-names = "du.0", "du.1", "dclkin.0", "dclkin.1";