diff options
| author | Gabriel Fernandez | 2016-08-29 14:26:00 +0200 |
|---|---|---|
| committer | Patrice Chotard | 2016-09-16 09:41:59 +0200 |
| commit | 665c8ec1222a6ede0615e9bcca914d1834da12de (patch) | |
| tree | d6e6e4897b395094af9d0f4a40c146b2a97d70a2 /arch/arm/boot/dts/stih418-clock.dtsi | |
| parent | ARM: DT: STi: stihxxx-b2120: Add DT nodes for STi audio card (diff) | |
| download | kernel-qcow2-linux-665c8ec1222a6ede0615e9bcca914d1834da12de.tar.gz kernel-qcow2-linux-665c8ec1222a6ede0615e9bcca914d1834da12de.tar.xz kernel-qcow2-linux-665c8ec1222a6ede0615e9bcca914d1834da12de.zip | |
ARM: dts: STiH4xx: Simplify clock binding of STiH4xx platforms
This patch simplifies the clock binding because we had too much detail.
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com>
Diffstat (limited to 'arch/arm/boot/dts/stih418-clock.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/stih418-clock.dtsi | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/arch/arm/boot/dts/stih418-clock.dtsi b/arch/arm/boot/dts/stih418-clock.dtsi index ae6d9978ea19..0fd0fa54132c 100644 --- a/arch/arm/boot/dts/stih418-clock.dtsi +++ b/arch/arm/boot/dts/stih418-clock.dtsi @@ -44,7 +44,7 @@ clockgen_a9_pll: clockgen-a9-pll { #clock-cells = <1>; - compatible = "st,stih418-plls-c28-a9", "st,clkgen-plls-c32"; + compatible = "st,stih418-clkgen-plla9"; clocks = <&clk_sysin>; @@ -98,7 +98,7 @@ clk_s_a0_pll: clk-s-a0-pll { #clock-cells = <1>; - compatible = "st,stih407-plls-c32-a0", "st,clkgen-plls-c32"; + compatible = "st,clkgen-pll0"; clocks = <&clk_sysin>; @@ -120,7 +120,7 @@ clk_s_c0_quadfs: clk-s-c0-quadfs@9103000 { #clock-cells = <1>; - compatible = "st,stih407-quadfs660-C", "st,quadfs"; + compatible = "st,quadfs-pll"; reg = <0x9103000 0x1000>; clocks = <&clk_sysin>; @@ -137,7 +137,7 @@ clk_s_c0_pll0: clk-s-c0-pll0 { #clock-cells = <1>; - compatible = "st,plls-c32-cx_0", "st,clkgen-plls-c32"; + compatible = "st,clkgen-pll0"; clocks = <&clk_sysin>; @@ -146,7 +146,7 @@ clk_s_c0_pll1: clk-s-c0-pll1 { #clock-cells = <1>; - compatible = "st,plls-c32-cx_1", "st,clkgen-plls-c32"; + compatible = "st,clkgen-pll1"; clocks = <&clk_sysin>; @@ -212,7 +212,7 @@ clk_s_d0_quadfs: clk-s-d0-quadfs@9104000 { #clock-cells = <1>; - compatible = "st,stih407-quadfs660-D", "st,quadfs"; + compatible = "st,quadfs"; reg = <0x9104000 0x1000>; clocks = <&clk_sysin>; @@ -248,7 +248,7 @@ clk_s_d2_quadfs: clk-s-d2-quadfs@9106000 { #clock-cells = <1>; - compatible = "st,stih407-quadfs660-D", "st,quadfs"; + compatible = "st,quadfs"; reg = <0x9106000 0x1000>; clocks = <&clk_sysin>; @@ -309,7 +309,7 @@ clk_s_d3_quadfs: clk-s-d3-quadfs@9107000 { #clock-cells = <1>; - compatible = "st,stih407-quadfs660-D", "st,quadfs"; + compatible = "st,quadfs"; reg = <0x9107000 0x1000>; clocks = <&clk_sysin>; |