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| author | Russell King | 2014-05-27 21:34:28 +0200 |
|---|---|---|
| committer | Russell King | 2014-06-02 10:23:54 +0200 |
| commit | ca8f0b0a545f55b3dc6877cda24d609a8979c951 (patch) | |
| tree | 6f6800bbf78f1b81a1d6bb73d84f380e08113c17 /arch/arm/kernel/setup.c | |
| parent | ARM: consolidate last remaining open-coded alignment trap enable (diff) | |
| download | kernel-qcow2-linux-ca8f0b0a545f55b3dc6877cda24d609a8979c951.tar.gz kernel-qcow2-linux-ca8f0b0a545f55b3dc6877cda24d609a8979c951.tar.xz kernel-qcow2-linux-ca8f0b0a545f55b3dc6877cda24d609a8979c951.zip | |
ARM: ensure C page table setup code follows assembly code
Fix a long standing bug where, for ARMv6+, we don't fully ensure that
the C code sets the same cache policy as the assembly code. This was
introduced partially by commit 11179d8ca28d ([ARM] 4497/1: Only allow
safe cache configurations on ARMv6 and later) and also by adding SMP
support.
This patch sets the default cache policy based on the flags used by the
assembly code, and then ensures that when a cache policy command line
argument is used, we verify that on ARMv6, it matches the initial setup.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/kernel/setup.c')
| -rw-r--r-- | arch/arm/kernel/setup.c | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c index df21f9f98945..f5120ca08671 100644 --- a/arch/arm/kernel/setup.c +++ b/arch/arm/kernel/setup.c @@ -72,6 +72,7 @@ static int __init fpe_setup(char *line) __setup("fpe=", fpe_setup); #endif +extern void init_default_cache_policy(unsigned long); extern void paging_init(const struct machine_desc *desc); extern void early_paging_init(const struct machine_desc *, struct proc_info_list *); @@ -603,7 +604,9 @@ static void __init setup_processor(void) #ifndef CONFIG_ARM_THUMB elf_hwcap &= ~(HWCAP_THUMB | HWCAP_IDIVT); #endif - +#ifdef CONFIG_MMU + init_default_cache_policy(list->__cpu_mm_mmu_flags); +#endif erratum_a15_798181_init(); feat_v6_fixup(); |