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authorSantosh Shilimkar2012-09-13 06:14:34 +0200
committerTony Lindgren2012-09-13 06:14:34 +0200
commitecc335fc970bb9249c6954cc958f24cec51f52d2 (patch)
tree258c4060eca5ac954f552a2e64094f267d379472 /arch/arm/mach-omap2/omap-wakeupgen.c
parentgpio/omap: fix possible memory leak in omap2_gpio_dev_init() (diff)
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ARM: OMAP4: wakeupgen: Fix the typo in AUXCOREBOOT register save
The wakeupgen context-save code reads AUXCOREBOOT0 register instead of AUXCOREBOOT1 register contents while saving AUXCOREBOOT1. Fix the same. Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
Diffstat (limited to 'arch/arm/mach-omap2/omap-wakeupgen.c')
-rw-r--r--arch/arm/mach-omap2/omap-wakeupgen.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/mach-omap2/omap-wakeupgen.c b/arch/arm/mach-omap2/omap-wakeupgen.c
index 05fdebfaa195..c3795c27a0b1 100644
--- a/arch/arm/mach-omap2/omap-wakeupgen.c
+++ b/arch/arm/mach-omap2/omap-wakeupgen.c
@@ -229,7 +229,7 @@ static inline void omap4_irq_save_context(void)
/* Save AuxBoot* registers */
val = __raw_readl(wakeupgen_base + OMAP_AUX_CORE_BOOT_0);
__raw_writel(val, sar_base + AUXCOREBOOT0_OFFSET);
- val = __raw_readl(wakeupgen_base + OMAP_AUX_CORE_BOOT_0);
+ val = __raw_readl(wakeupgen_base + OMAP_AUX_CORE_BOOT_1);
__raw_writel(val, sar_base + AUXCOREBOOT1_OFFSET);
/* Save SyncReq generation logic */