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| author | Marc Zyngier | 2015-01-17 11:21:08 +0100 |
|---|---|---|
| committer | Tony Lindgren | 2015-01-17 17:56:12 +0100 |
| commit | 0fb22a8fb7f3bc1b00a36d4a97ce4f93191f7559 (patch) | |
| tree | 888e0445b2ceab5ec0774990e963defe7858f926 /arch/arm/mach-omap2/prcm-common.h | |
| parent | arm: boot: dts: dra7: enable dwc3 suspend PHY quirk (diff) | |
| download | kernel-qcow2-linux-0fb22a8fb7f3bc1b00a36d4a97ce4f93191f7559.tar.gz kernel-qcow2-linux-0fb22a8fb7f3bc1b00a36d4a97ce4f93191f7559.tar.xz kernel-qcow2-linux-0fb22a8fb7f3bc1b00a36d4a97ce4f93191f7559.zip | |
ARM: OMAP: Work around hardcoded interrupts
Commit 9a1091ef0017 ("irqchip: gic: Support hierarchy irq domain")
changed the GIC driver to use a non-legacy IRQ domain on DT
platforms. This patch assumes that DT-driven systems are getting
all of their interrupts from device tree.
Turns out that OMAP has quite a few hidden gems, and still uses
hardcoded interrupts despite having fairly complete DTs.
This patch attempts to work around these by offering a translation
method that can be called directly from the hwmod code, if present.
The same hack is sprinkled over PRCM and TWL.
It isn't pretty, but it seems to do the job without having to add
more hacks to the interrupt controller code.
Tested on OMAP4 (Panda-ES) and OMAP5 (UEVM5432).
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Acked-by: Nishanth Menon <nm@ti.com>
[tony@atomide.com: updated to fix make randconfig issue]
Signed-off-by: Tony Lindgren <tony@atomide.com>
Diffstat (limited to 'arch/arm/mach-omap2/prcm-common.h')
| -rw-r--r-- | arch/arm/mach-omap2/prcm-common.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/arm/mach-omap2/prcm-common.h b/arch/arm/mach-omap2/prcm-common.h index a8e4b582c527..6163d66102a3 100644 --- a/arch/arm/mach-omap2/prcm-common.h +++ b/arch/arm/mach-omap2/prcm-common.h @@ -498,6 +498,7 @@ struct omap_prcm_irq_setup { u8 nr_irqs; const struct omap_prcm_irq *irqs; int irq; + unsigned int (*xlate_irq)(unsigned int); void (*read_pending_irqs)(unsigned long *events); void (*ocp_barrier)(void); void (*save_and_clear_irqen)(u32 *saved_mask); |