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| author | James Morse | 2018-01-15 20:38:59 +0100 |
|---|---|---|
| committer | Catalin Marinas | 2018-01-16 16:07:12 +0100 |
| commit | 68ddbf09ec5a888ec850edd7e7438d2daf069c56 (patch) | |
| tree | 07f56625a64473270c90dcfc8c74589540b81e96 /arch/arm64/mm | |
| parent | arm64: Unconditionally enable IESB on exception entry/return for firmware-first (diff) | |
| download | kernel-qcow2-linux-68ddbf09ec5a888ec850edd7e7438d2daf069c56.tar.gz kernel-qcow2-linux-68ddbf09ec5a888ec850edd7e7438d2daf069c56.tar.xz kernel-qcow2-linux-68ddbf09ec5a888ec850edd7e7438d2daf069c56.zip | |
arm64: kernel: Prepare for a DISR user
KVM would like to consume any pending SError (or RAS error) after guest
exit. Today it has to unmask SError and use dsb+isb to synchronise the
CPU. With the RAS extensions we can use ESB to synchronise any pending
SError.
Add the necessary macros to allow DISR to be read and converted to an
ESR.
We clear the DISR register when we enable the RAS cpufeature, and the
kernel has not executed any ESB instructions. Any value we find in DISR
must have belonged to firmware. Executing an ESB instruction is the
only way to update DISR, so we can expect firmware to have handled
any deferred SError. By the same logic we clear DISR in the idle path.
Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: James Morse <james.morse@arm.com>
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Diffstat (limited to 'arch/arm64/mm')
| -rw-r--r-- | arch/arm64/mm/proc.S | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/arch/arm64/mm/proc.S b/arch/arm64/mm/proc.S index ec4c3d82b4d6..05e4ae934b23 100644 --- a/arch/arm64/mm/proc.S +++ b/arch/arm64/mm/proc.S @@ -132,6 +132,11 @@ alternative_endif ubfx x11, x11, #1, #1 msr oslar_el1, x11 reset_pmuserenr_el0 x0 // Disable PMU access from EL0 + +alternative_if ARM64_HAS_RAS_EXTN + msr_s SYS_DISR_EL1, xzr +alternative_else_nop_endif + isb ret ENDPROC(cpu_do_resume) |