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| author | Paul Burton | 2014-07-14 11:32:14 +0200 |
|---|---|---|
| committer | Ralf Baechle | 2014-08-02 00:06:45 +0200 |
| commit | 1f6c52ff7225789d20c1d69883f263d502b7eda7 (patch) | |
| tree | c97ef1d8e597e9b046b6adecf305df488d6543c2 /arch/mips/include | |
| parent | MIPS: define MAAR register accessors & bits (diff) | |
| download | kernel-qcow2-linux-1f6c52ff7225789d20c1d69883f263d502b7eda7.tar.gz kernel-qcow2-linux-1f6c52ff7225789d20c1d69883f263d502b7eda7.tar.xz kernel-qcow2-linux-1f6c52ff7225789d20c1d69883f263d502b7eda7.zip | |
MIPS: detect presence of MAARs
Detect the presence of MAAR using the MRP bit in Config5, and record
that presence using a CPU option bit. A cpu_has_maar macro will then
allow code to conditionalise upon the presence of MAARs.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/7330/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/include')
| -rw-r--r-- | arch/mips/include/asm/cpu-features.h | 3 | ||||
| -rw-r--r-- | arch/mips/include/asm/cpu.h | 1 |
2 files changed, 4 insertions, 0 deletions
diff --git a/arch/mips/include/asm/cpu-features.h b/arch/mips/include/asm/cpu-features.h index eeb5400ed4ee..e079598ae051 100644 --- a/arch/mips/include/asm/cpu-features.h +++ b/arch/mips/include/asm/cpu-features.h @@ -35,6 +35,9 @@ #ifndef cpu_has_rixiex #define cpu_has_rixiex (cpu_data[0].options & MIPS_CPU_RIXIEX) #endif +#ifndef cpu_has_maar +#define cpu_has_maar (cpu_data[0].options & MIPS_CPU_MAAR) +#endif /* * For the moment we don't consider R6000 and R8000 so we can assume that diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h index 7ba2a035ad86..dfdc77ed1839 100644 --- a/arch/mips/include/asm/cpu.h +++ b/arch/mips/include/asm/cpu.h @@ -367,6 +367,7 @@ enum cpu_type_enum { #define MIPS_CPU_EVA 0x80000000ull /* CPU supports Enhanced Virtual Addressing */ #define MIPS_CPU_HTW 0x100000000ull /* CPU support Hardware Page Table Walker */ #define MIPS_CPU_RIXIEX 0x200000000ull /* CPU has unique exception codes for {Read, Execute}-Inhibit exceptions */ +#define MIPS_CPU_MAAR 0x400000000ull /* MAAR(I) registers are present */ /* * CPU ASE encodings |