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| author | Huacai Chen | 2014-06-26 05:41:30 +0200 |
|---|---|---|
| committer | Ralf Baechle | 2014-07-30 21:47:00 +0200 |
| commit | e7841be50fe2b8751a51a068b8cdcdcb6611e354 (patch) | |
| tree | d0ffedc83975c17cfa3357ebcb806a2fa86d3566 /arch/mips/include | |
| parent | MIPS: Add numa api support (diff) | |
| download | kernel-qcow2-linux-e7841be50fe2b8751a51a068b8cdcdcb6611e354.tar.gz kernel-qcow2-linux-e7841be50fe2b8751a51a068b8cdcdcb6611e354.tar.xz kernel-qcow2-linux-e7841be50fe2b8751a51a068b8cdcdcb6611e354.zip | |
MIPS: Add Loongson-3B support
Loongson-3B is a 8-cores processor. In general it looks like there are
two Loongson-3A integrated in one chip: 8 cores are separated into two
groups (two NUMA node), each node has its own local memory.
Of course there are some differences between one Loongson-3B and two
Loongson-3A. E.g., the base addresses of IPI registers of each node are
not the same; Loongson-3A use ChipConfig register to enable/disable
clock, but Loongson-3B use FreqControl register instead.
There are two revision of Loongson-3B, the first revision is called as
Loongson-3B1000, whose frequency is 1GHz and has a PRid 0x6306, the
second revision is called as Loongson-3B1500, whose frequency is 1.5GHz
and has a PRid 0x6307. Both revisions has a bug that clock cannot be
disabled at runtime, but this will be fixed in future.
Signed-off-by: Huacai Chen <chenhc@lemote.com>
Cc: John Crispin <john@phrozen.org>
Cc: Steven J. Hill <Steven.Hill@imgtec.com>
Cc: Aurelien Jarno <aurelien@aurel32.net>
Cc: linux-mips@linux-mips.org
Cc: Fuxin Zhang <zhangfx@lemote.com>
Cc: Zhangjin Wu <wuzhangjin@gmail.com>
Patchwork: https://patchwork.linux-mips.org/patch/7188/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/include')
| -rw-r--r-- | arch/mips/include/asm/cpu.h | 2 | ||||
| -rw-r--r-- | arch/mips/include/asm/mach-loongson/boot_param.h | 1 | ||||
| -rw-r--r-- | arch/mips/include/asm/mach-loongson/loongson.h | 4 |
3 files changed, 7 insertions, 0 deletions
diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h index 129d08701e91..abf7e005b98f 100644 --- a/arch/mips/include/asm/cpu.h +++ b/arch/mips/include/asm/cpu.h @@ -233,6 +233,8 @@ #define PRID_REV_LOONGSON2E 0x0002 #define PRID_REV_LOONGSON2F 0x0003 #define PRID_REV_LOONGSON3A 0x0005 +#define PRID_REV_LOONGSON3B_R1 0x0006 +#define PRID_REV_LOONGSON3B_R2 0x0007 /* * Older processors used to encode processor version and revision in two diff --git a/arch/mips/include/asm/mach-loongson/boot_param.h b/arch/mips/include/asm/mach-loongson/boot_param.h index 8b06c96cce1f..3388fc53599e 100644 --- a/arch/mips/include/asm/mach-loongson/boot_param.h +++ b/arch/mips/include/asm/mach-loongson/boot_param.h @@ -163,4 +163,5 @@ struct loongson_system_configuration { extern struct efi_memory_map_loongson *loongson_memmap; extern struct loongson_system_configuration loongson_sysconf; +extern int cpuhotplug_workaround; #endif diff --git a/arch/mips/include/asm/mach-loongson/loongson.h b/arch/mips/include/asm/mach-loongson/loongson.h index a1c76caa7436..92bf76c21441 100644 --- a/arch/mips/include/asm/mach-loongson/loongson.h +++ b/arch/mips/include/asm/mach-loongson/loongson.h @@ -255,6 +255,10 @@ static inline void do_perfcnt_IRQ(void) extern u64 loongson_chipcfg[MAX_PACKAGES]; #define LOONGSON_CHIPCFG(id) (*(volatile u32 *)(loongson_chipcfg[id])) +/* Freq Control register of each physical cpu package, PRid >= Loongson-3B */ +extern u64 loongson_freqctrl[MAX_PACKAGES]; +#define LOONGSON_FREQCTRL(id) (*(volatile u32 *)(loongson_freqctrl[id])) + /* pcimap */ #define LOONGSON_PCIMAP_PCIMAP_LO0 0x0000003f |