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| author | Paul Mackerras | 2017-08-30 06:12:29 +0200 |
|---|---|---|
| committer | Michael Ellerman | 2017-09-01 08:39:49 +0200 |
| commit | f1bbb99f41e06d5ba93ea8eafacd96a7a71d0c7d (patch) | |
| tree | 712760be9aa2d0a6bbc96013b1e47195056ccd62 /arch/powerpc/lib/sstep.c | |
| parent | powerpc/64: Fix update forms of loads and stores to write 64-bit EA (diff) | |
| download | kernel-qcow2-linux-f1bbb99f41e06d5ba93ea8eafacd96a7a71d0c7d.tar.gz kernel-qcow2-linux-f1bbb99f41e06d5ba93ea8eafacd96a7a71d0c7d.tar.xz kernel-qcow2-linux-f1bbb99f41e06d5ba93ea8eafacd96a7a71d0c7d.zip | |
powerpc: Fix emulation of the isel instruction
The case added for the isel instruction was added inside a switch
statement which uses the 10-bit minor opcode field in the 0x7fe
bits of the instruction word. However, for the isel instruction,
the minor opcode field is only the 0x3e bits, and the 0x7c0 bits
are used for the "BC" field, which indicates which CR bit to use
to select the result.
Therefore, for the isel emulation to work correctly when BC != 0,
we need to match on ((instr >> 1) & 0x1f) == 15). To do this, we
pull the isel case out of the switch statement and put it in an
if statement of its own.
Fixes: e27f71e5ff3c ("powerpc/lib/sstep: Add isel instruction emulation")
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Diffstat (limited to 'arch/powerpc/lib/sstep.c')
| -rw-r--r-- | arch/powerpc/lib/sstep.c | 18 |
1 files changed, 10 insertions, 8 deletions
diff --git a/arch/powerpc/lib/sstep.c b/arch/powerpc/lib/sstep.c index 89e5c26e2860..00dae7b7e785 100644 --- a/arch/powerpc/lib/sstep.c +++ b/arch/powerpc/lib/sstep.c @@ -1216,6 +1216,16 @@ int analyse_instr(struct instruction_op *op, const struct pt_regs *regs, return 0; case 31: + /* isel occupies 32 minor opcodes */ + if (((instr >> 1) & 0x1f) == 15) { + mb = (instr >> 6) & 0x1f; /* bc field */ + val = (regs->ccr >> (31 - mb)) & 1; + val2 = (ra) ? regs->gpr[ra] : 0; + + op->val = (val) ? val2 : regs->gpr[rb]; + goto compute_done; + } + switch ((instr >> 1) & 0x3ff) { case 4: /* tw */ if (rd == 0x1f || @@ -1441,14 +1451,6 @@ int analyse_instr(struct instruction_op *op, const struct pt_regs *regs, /* * Logical instructions */ - case 15: /* isel */ - mb = (instr >> 6) & 0x1f; /* bc */ - val = (regs->ccr >> (31 - mb)) & 1; - val2 = (ra) ? regs->gpr[ra] : 0; - - op->val = (val) ? val2 : regs->gpr[rb]; - goto compute_done; - case 26: /* cntlzw */ op->val = __builtin_clz((unsigned int) regs->gpr[rd]); goto logical_done; |