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| author | Michael Ellerman | 2007-10-15 11:34:36 +0200 |
|---|---|---|
| committer | Jeff Garzik | 2007-10-15 20:29:49 +0200 |
| commit | 83f34df4e7c8794a5a81ede663fe184f4201308a (patch) | |
| tree | c109c113ee02c5d656cd1b211ba2bc67d5dfd270 /arch | |
| parent | Use dcr_host_t.base in ibm_emac_mal (diff) | |
| download | kernel-qcow2-linux-83f34df4e7c8794a5a81ede663fe184f4201308a.tar.gz kernel-qcow2-linux-83f34df4e7c8794a5a81ede663fe184f4201308a.tar.xz kernel-qcow2-linux-83f34df4e7c8794a5a81ede663fe184f4201308a.zip | |
Add dcr_host_t.base in dcr_read()/dcr_write()
Now that all users of dcr_read()/dcr_write() add the dcr_host_t.base, we
can save them the trouble and do it in dcr_read()/dcr_write().
As some background to why we just went through all this jiggery-pokery,
benh sayeth:
Initially the goal of the dcr_read/dcr_write routines was to operate like
mfdcr/mtdcr which take absolute DCR numbers. The reason is that on 4xx
hardware, indirect DCR access is a pain (goes through a table of
instructions) and it's useful to have the compiler resolve an absolute DCR
inline.
We decided that wasn't worth the API bastardisation since most places
where absolute DCR values are used are low level 4xx-only code which may
as well continue using mfdcr/mtdcr, while the new API is designed for
device "instances" that can exist on 4xx and Axon type platforms and may
be located at variable DCR offsets.
Signed-off-by: Michael Ellerman <michael@ellerman.id.au>
Signed-off-by: Jeff Garzik <jeff@garzik.org>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/powerpc/platforms/cell/axon_msi.c | 4 | ||||
| -rw-r--r-- | arch/powerpc/sysdev/mpic.c | 4 |
2 files changed, 4 insertions, 4 deletions
diff --git a/arch/powerpc/platforms/cell/axon_msi.c b/arch/powerpc/platforms/cell/axon_msi.c index 1245b2f517bb..aca15007a01c 100644 --- a/arch/powerpc/platforms/cell/axon_msi.c +++ b/arch/powerpc/platforms/cell/axon_msi.c @@ -77,12 +77,12 @@ static void msic_dcr_write(struct axon_msic *msic, unsigned int dcr_n, u32 val) { pr_debug("axon_msi: dcr_write(0x%x, 0x%x)\n", val, dcr_n); - dcr_write(msic->dcr_host, msic->dcr_host.base + dcr_n, val); + dcr_write(msic->dcr_host, dcr_n, val); } static u32 msic_dcr_read(struct axon_msic *msic, unsigned int dcr_n) { - return dcr_read(msic->dcr_host, msic->dcr_host.base + dcr_n); + return dcr_read(msic->dcr_host, dcr_n); } static void axon_msi_cascade(unsigned int irq, struct irq_desc *desc) diff --git a/arch/powerpc/sysdev/mpic.c b/arch/powerpc/sysdev/mpic.c index 893e65439e85..e47938899a92 100644 --- a/arch/powerpc/sysdev/mpic.c +++ b/arch/powerpc/sysdev/mpic.c @@ -156,7 +156,7 @@ static inline u32 _mpic_read(enum mpic_reg_type type, switch(type) { #ifdef CONFIG_PPC_DCR case mpic_access_dcr: - return dcr_read(rb->dhost, rb->dhost.base + reg); + return dcr_read(rb->dhost, reg); #endif case mpic_access_mmio_be: return in_be32(rb->base + (reg >> 2)); @@ -173,7 +173,7 @@ static inline void _mpic_write(enum mpic_reg_type type, switch(type) { #ifdef CONFIG_PPC_DCR case mpic_access_dcr: - return dcr_write(rb->dhost, rb->dhost.base + reg, value); + return dcr_write(rb->dhost, reg, value); #endif case mpic_access_mmio_be: return out_be32(rb->base + (reg >> 2), value); |