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| author | Linus Walleij | 2016-08-22 11:16:57 +0200 |
|---|---|---|
| committer | Linus Walleij | 2016-08-31 09:30:15 +0200 |
| commit | 49eb1efadc47f49b0f43a4725f116fa61aba206b (patch) | |
| tree | 4dd71304932d3cb093b3386639d8dec73434b360 /arch | |
| parent | ARM: dts: set the 24MHz xtal as parent of the UART clock (diff) | |
| download | kernel-qcow2-linux-49eb1efadc47f49b0f43a4725f116fa61aba206b.tar.gz kernel-qcow2-linux-49eb1efadc47f49b0f43a4725f116fa61aba206b.tar.xz kernel-qcow2-linux-49eb1efadc47f49b0f43a4725f116fa61aba206b.zip | |
ARM: dts: add the Integrator/AP baseboard clocks
The two clocks present on the Integrator/AP baseboard and
accessible through its system controller is the PCIv3 bridge
clock and the PCI bus clock. Define the proper device tree
nodes for these.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/boot/dts/integratorap.dts | 21 |
1 files changed, 21 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/integratorap.dts b/arch/arm/boot/dts/integratorap.dts index 33b253d5e244..16266722ce7c 100644 --- a/arch/arm/boot/dts/integratorap.dts +++ b/arch/arm/boot/dts/integratorap.dts @@ -48,6 +48,27 @@ interrupt-parent = <&pic>; /* These are the logical module IRQs */ interrupts = <9>, <10>, <11>, <12>; + + /* + * SYSCLK clocks PCIv3 bridge, system controller and the + * logic modules. + */ + sysclk: apsys@24M { + compatible = "arm,syscon-icst525-integratorap-sys"; + #clock-cells = <0>; + lock-offset = <0x1c>; + vco-offset = <0x04>; + clocks = <&xtal24mhz>; + }; + + /* One-bit control for the PCI bus clock (33 or 25 MHz) */ + pciclk: pciclk@24M { + compatible = "arm,syscon-icst525-integratorap-pci"; + #clock-cells = <0>; + lock-offset = <0x1c>; + vco-offset = <0x04>; + clocks = <&xtal24mhz>; + }; }; timer0: timer@13000000 { |