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| author | Suravee Suthikulpanit | 2018-06-27 17:31:22 +0200 |
|---|---|---|
| committer | Joerg Roedel | 2018-07-06 14:43:47 +0200 |
| commit | 90fcffd9cf5e7cc593169f529799f3e3c5437e75 (patch) | |
| tree | 8cea3c13a5a83e5bf4667e05888ec7ac919f8556 /crypto/ansi_cprng.c | |
| parent | iommu/amd: Add support for higher 64-bit IOMMU Control Register (diff) | |
| download | kernel-qcow2-linux-90fcffd9cf5e7cc593169f529799f3e3c5437e75.tar.gz kernel-qcow2-linux-90fcffd9cf5e7cc593169f529799f3e3c5437e75.tar.xz kernel-qcow2-linux-90fcffd9cf5e7cc593169f529799f3e3c5437e75.zip | |
iommu/amd: Add support for IOMMU XT mode
The AMD IOMMU XT mode enables interrupt remapping with 32-bit destination
APIC ID, which is required for x2APIC. The feature is available when
the XTSup bit is set in the IOMMU Extended Feature register
and/or the IVHD Type 10h IOMMU Feature Reporting field.
For more information, please see section "IOMMU x2APIC Support" of
the AMD I/O Virtualization Technology (IOMMU) Specification.
Cc: Joerg Roedel <jroedel@suse.de>
Signed-off-by: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
Signed-off-by: Joerg Roedel <jroedel@suse.de>
Diffstat (limited to 'crypto/ansi_cprng.c')
0 files changed, 0 insertions, 0 deletions