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authorAlex Deucher2017-03-30 19:03:07 +0200
committerAlex Deucher2017-04-06 19:26:47 +0200
commitfcf17a43ffd3b248d03b582b834367c45e9e8f59 (patch)
treecacfc33ab0997739f2ff8e5233a85cfe181d72c3 /drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
parentdrm/amdgpu: cleanup VMHUB bit definitions v2 (diff)
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drm/amdgpu/gfx8: KIQ is also disabled when MEC is disabled
Set the ready flag to reflect this. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c')
-rw-r--r--drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c1
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index e0fa0d30e162..2e0f55635579 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -4565,6 +4565,7 @@ static void gfx_v8_0_cp_compute_enable(struct amdgpu_device *adev, bool enable)
WREG32(mmCP_MEC_CNTL, (CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK));
for (i = 0; i < adev->gfx.num_compute_rings; i++)
adev->gfx.compute_ring[i].ready = false;
+ adev->gfx.kiq.ring.ready = false;
}
udelay(50);
}