diff options
| author | Leo (Hanghong) Ma | 2019-01-24 21:07:52 +0100 |
|---|---|---|
| committer | Greg Kroah-Hartman | 2019-02-27 10:09:01 +0100 |
| commit | 0329973ec999114da5277284c24f64299da68985 (patch) | |
| tree | 6aa67d71f8870bd09b9c2c9dce0bd2e397432805 /drivers/gpu/drm/amd | |
| parent | drm/i915/fbdev: Actually configure untiled displays (diff) | |
| download | kernel-qcow2-linux-0329973ec999114da5277284c24f64299da68985.tar.gz kernel-qcow2-linux-0329973ec999114da5277284c24f64299da68985.tar.xz kernel-qcow2-linux-0329973ec999114da5277284c24f64299da68985.zip | |
drm/amd/display: Fix MST reboot/poweroff sequence
commit d2f0b53bda3193874f3905bc839888f895d1c0cf upstream.
[Why]
drm_dp_mst_topology_mgr_suspend() is added into the new reboot
sequence, which disables the UP request at the beginning.
Therefore sideband messages are blocked.
[How]
Finish MST sideband message transaction before UP request is
suppressed.
Signed-off-by: Leo (Hanghong) Ma <hanghong.ma@amd.com>
Reviewed-by: Roman Li <Roman.Li@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'drivers/gpu/drm/amd')
| -rw-r--r-- | drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index a851bb07443f..c5ba9128b736 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -624,12 +624,13 @@ static int dm_suspend(void *handle) struct amdgpu_display_manager *dm = &adev->dm; int ret = 0; + WARN_ON(adev->dm.cached_state); + adev->dm.cached_state = drm_atomic_helper_suspend(adev->ddev); + s3_handle_mst(adev->ddev, true); amdgpu_dm_irq_suspend(adev); - WARN_ON(adev->dm.cached_state); - adev->dm.cached_state = drm_atomic_helper_suspend(adev->ddev); dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D3); |