diff options
| author | Mika Kuoppala | 2015-10-30 16:54:47 +0100 |
|---|---|---|
| committer | Ville Syrjälä | 2015-11-09 18:16:19 +0100 |
| commit | 6fb403de3620deacf1180d727d21875d07c7464a (patch) | |
| tree | 01bbf9680726f4b322b3e26f9a9d0c54bb251389 /drivers/gpu/drm/i915/i915_debugfs.c | |
| parent | drm/i915/bxt: Expose DC5 entry count (diff) | |
| download | kernel-qcow2-linux-6fb403de3620deacf1180d727d21875d07c7464a.tar.gz kernel-qcow2-linux-6fb403de3620deacf1180d727d21875d07c7464a.tar.xz kernel-qcow2-linux-6fb403de3620deacf1180d727d21875d07c7464a.zip | |
drm/i915: Add csr programming registers to dmc debugfs entry
We check these to determine firmware loading status. Include
them to help to debug causes of firmware loading fails.
v2: Move all CSR specific registers to i915_reg.h (Ville)
v3: Rebase
v4: Rebase (RPM ref)
Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1446220487-32691-1-git-send-email-mika.kuoppala@intel.com
Tested-by: Daniel Stone <daniels@collabora.com> # SKL
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Diffstat (limited to 'drivers/gpu/drm/i915/i915_debugfs.c')
| -rw-r--r-- | drivers/gpu/drm/i915/i915_debugfs.c | 11 |
1 files changed, 8 insertions, 3 deletions
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index 8096e96c7d35..e9ecabf79199 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -2802,17 +2802,17 @@ static int i915_dmc_info(struct seq_file *m, void *unused) csr = &dev_priv->csr; + intel_runtime_pm_get(dev_priv); + seq_printf(m, "fw loaded: %s\n", yesno(csr->dmc_payload != NULL)); seq_printf(m, "path: %s\n", csr->fw_path); if (!csr->dmc_payload) - return 0; + goto out; seq_printf(m, "version: %d.%d\n", CSR_VERSION_MAJOR(csr->version), CSR_VERSION_MINOR(csr->version)); - intel_runtime_pm_get(dev_priv); - if (IS_SKYLAKE(dev) && csr->version >= CSR_VERSION(1, 6)) { seq_printf(m, "DC3 -> DC5 count: %d\n", I915_READ(SKL_CSR_DC3_DC5_COUNT)); @@ -2823,6 +2823,11 @@ static int i915_dmc_info(struct seq_file *m, void *unused) I915_READ(BXT_CSR_DC3_DC5_COUNT)); } +out: + seq_printf(m, "program base: 0x%08x\n", I915_READ(CSR_PROGRAM(0))); + seq_printf(m, "ssp base: 0x%08x\n", I915_READ(CSR_SSP_BASE)); + seq_printf(m, "htp: 0x%08x\n", I915_READ(CSR_HTP_SKL)); + intel_runtime_pm_put(dev_priv); return 0; |