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| author | Ville Syrjälä | 2014-04-09 12:28:01 +0200 |
|---|---|---|
| committer | Daniel Vetter | 2014-05-06 18:29:34 +0200 |
| commit | ee0ce4784acc0b17c177c0274cb6fc096d977829 (patch) | |
| tree | 2c4d65b5eca42d26f7b0f006dd6e642bca4511f8 /drivers/gpu/drm/i915/i915_gem_gtt.h | |
| parent | drm/i915: Remove useless checks from primary enable/disable (diff) | |
| download | kernel-qcow2-linux-ee0ce4784acc0b17c177c0274cb6fc096d977829.tar.gz kernel-qcow2-linux-ee0ce4784acc0b17c177c0274cb6fc096d977829.tar.xz kernel-qcow2-linux-ee0ce4784acc0b17c177c0274cb6fc096d977829.zip | |
drm/i915/chv: PPAT setup for Cherryview
Ignore the cache bits in PPAT and just set the snoop bit where
appropriate. BDW WB is mapped to snooped access, while all other
modes are mapped to non-snooped access.
The hardware supposedly ignores everything except the snoop bit
in the PPAT entries.
Additionally the hardware actually enforces snooping for all
page table accesses, and thus the snoop bit is ignored for PDEs.
v2: Rebased on top of the bdw resume fix to reload the ppat entries.
v3: Rebase on top of the i915_gem_gtt.h header extraction.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> (v1)
Acked-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Rafael Barbalho <rafael.barbalho@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/i915_gem_gtt.h')
| -rw-r--r-- | drivers/gpu/drm/i915/i915_gem_gtt.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h b/drivers/gpu/drm/i915/i915_gem_gtt.h index b5e8ac0f5ce4..cfca023c4076 100644 --- a/drivers/gpu/drm/i915/i915_gem_gtt.h +++ b/drivers/gpu/drm/i915/i915_gem_gtt.h @@ -95,6 +95,7 @@ typedef gen8_gtt_pte_t gen8_ppgtt_pde_t; #define PPAT_CACHED_INDEX _PAGE_PAT /* WB LLCeLLC */ #define PPAT_DISPLAY_ELLC_INDEX _PAGE_PCD /* WT eLLC */ +#define CHV_PPAT_SNOOP (1<<6) #define GEN8_PPAT_AGE(x) (x<<4) #define GEN8_PPAT_LLCeLLC (3<<2) #define GEN8_PPAT_LLCELLC (2<<2) |