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| author | Chris Wilson | 2017-11-20 11:20:01 +0100 |
|---|---|---|
| committer | Chris Wilson | 2017-11-20 16:56:16 +0100 |
| commit | 2113184c6f6749f6e4e86a42894f67a50ead6775 (patch) | |
| tree | a4b4b8737f21af6f418e8bece61c9f525656c4d6 /drivers/gpu/drm/i915/i915_gem_request.c | |
| parent | drm/i915/perf: replace .reg accesses with i915_mmio_reg_offset (diff) | |
| download | kernel-qcow2-linux-2113184c6f6749f6e4e86a42894f67a50ead6775.tar.gz kernel-qcow2-linux-2113184c6f6749f6e4e86a42894f67a50ead6775.tar.xz kernel-qcow2-linux-2113184c6f6749f6e4e86a42894f67a50ead6775.zip | |
drm/i915: Pull the unconditional GPU cache invalidation into request construction
As the request will, in the following patch, implicitly invoke a
context-switch on construction, we should precede that with a GPU TLB
invalidation. Also, even before using GGTT, we always want to invalidate
the TLBs for any updates (as well as the ppgtt invalidates that are
unconditionally applied by execbuf). Since we almost always require the
TLB invalidate, do it unconditionally on request allocation and so we can
remove it from all other paths.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20171120102002.22254-1-chris@chris-wilson.co.uk
Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Diffstat (limited to 'drivers/gpu/drm/i915/i915_gem_request.c')
| -rw-r--r-- | drivers/gpu/drm/i915/i915_gem_request.c | 24 |
1 files changed, 19 insertions, 5 deletions
diff --git a/drivers/gpu/drm/i915/i915_gem_request.c b/drivers/gpu/drm/i915/i915_gem_request.c index e0d6221022a8..91eae1b20c42 100644 --- a/drivers/gpu/drm/i915/i915_gem_request.c +++ b/drivers/gpu/drm/i915/i915_gem_request.c @@ -703,17 +703,31 @@ i915_gem_request_alloc(struct intel_engine_cs *engine, req->reserved_space = MIN_SPACE_FOR_ADD_REQUEST; GEM_BUG_ON(req->reserved_space < engine->emit_breadcrumb_sz); - ret = engine->request_alloc(req); - if (ret) - goto err_ctx; - - /* Record the position of the start of the request so that + /* + * Record the position of the start of the request so that * should we detect the updated seqno part-way through the * GPU processing the request, we never over-estimate the * position of the head. */ req->head = req->ring->emit; + /* Unconditionally invalidate GPU caches and TLBs. */ + ret = engine->emit_flush(req, EMIT_INVALIDATE); + if (ret) + goto err_ctx; + + ret = engine->request_alloc(req); + if (ret) { + /* + * Past the point-of-no-return. Since we may have updated + * global state after partially completing the request alloc, + * we need to commit any commands so far emitted in the + * request to the HW. + */ + __i915_add_request(req, false); + return ERR_PTR(ret); + } + /* Check that we didn't interrupt ourselves with a new request */ GEM_BUG_ON(req->timeline->seqno != req->fence.seqno); return req; |