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| author | Sagar Arun Kamble | 2017-03-11 03:37:01 +0100 |
|---|---|---|
| committer | Chris Wilson | 2017-03-12 13:59:11 +0100 |
| commit | 1f3b1fd386e6b8cde64e530a58264981e00bafa0 (patch) | |
| tree | 9896803bd266d3321226188a1fd91cef5ee82ee3 /drivers/gpu/drm/i915/i915_guc_submission.c | |
| parent | drm/i915: s/pm_intr_keep/pm_intrmsk_mbz (diff) | |
| download | kernel-qcow2-linux-1f3b1fd386e6b8cde64e530a58264981e00bafa0.tar.gz kernel-qcow2-linux-1f3b1fd386e6b8cde64e530a58264981e00bafa0.tar.xz kernel-qcow2-linux-1f3b1fd386e6b8cde64e530a58264981e00bafa0.zip | |
drm/i915/guc: Update rps.pm_intrmsk_mbz in guc_interrupts_capture/release
Different state is to be maintained for rps.pm_intrmsk_mbz for GuC and
Execlists. Updating it inside guc_interrupts_* routines as in those
routines GuC load/submission params are sanitized and it should not be set
based on HAS_GUC_SCHED during intel_irq_init.
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Oscar Mateo <oscar.mateo@intel.com>
Cc: Radoslaw Szwichtenberg <radoslaw.szwichtenberg@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1489199821-6707-3-git-send-email-sagar.a.kamble@intel.com
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Diffstat (limited to 'drivers/gpu/drm/i915/i915_guc_submission.c')
| -rw-r--r-- | drivers/gpu/drm/i915/i915_guc_submission.c | 26 |
1 files changed, 26 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c b/drivers/gpu/drm/i915/i915_guc_submission.c index 01b611cdb751..ca7723fd0f79 100644 --- a/drivers/gpu/drm/i915/i915_guc_submission.c +++ b/drivers/gpu/drm/i915/i915_guc_submission.c @@ -954,6 +954,28 @@ static void guc_interrupts_capture(struct drm_i915_private *dev_priv) I915_WRITE(GUC_BCS_RCS_IER, ~irqs); I915_WRITE(GUC_VCS2_VCS1_IER, ~irqs); I915_WRITE(GUC_WD_VECS_IER, ~irqs); + + /* + * The REDIRECT_TO_GUC bit of the PMINTRMSK register directs all + * (unmasked) PM interrupts to the GuC. All other bits of this + * register *disable* generation of a specific interrupt. + * + * 'pm_intrmsk_mbz' indicates bits that are NOT to be set when + * writing to the PM interrupt mask register, i.e. interrupts + * that must not be disabled. + * + * If the GuC is handling these interrupts, then we must not let + * the PM code disable ANY interrupt that the GuC is expecting. + * So for each ENABLED (0) bit in this register, we must SET the + * bit in pm_intrmsk_mbz so that it's left enabled for the GuC. + * GuC needs ARAT expired interrupt unmasked hence it is set in + * pm_intrmsk_mbz. + * + * Here we CLEAR REDIRECT_TO_GUC bit in pm_intrmsk_mbz, which will + * result in the register bit being left SET! + */ + dev_priv->rps.pm_intrmsk_mbz |= ARAT_EXPIRED_INTRMSK; + dev_priv->rps.pm_intrmsk_mbz &= ~GEN8_PMINTR_REDIRECT_TO_GUC; } int i915_guc_submission_enable(struct drm_i915_private *dev_priv) @@ -1014,6 +1036,10 @@ static void guc_interrupts_release(struct drm_i915_private *dev_priv) I915_WRITE(GUC_BCS_RCS_IER, 0); I915_WRITE(GUC_VCS2_VCS1_IER, 0); I915_WRITE(GUC_WD_VECS_IER, 0); + + dev_priv->rps.pm_intrmsk_mbz |= GEN8_PMINTR_REDIRECT_TO_GUC; + dev_priv->rps.pm_intrmsk_mbz &= ~ARAT_EXPIRED_INTRMSK; + } void i915_guc_submission_disable(struct drm_i915_private *dev_priv) |