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| author | Dhinakaran Pandiyan | 2018-05-11 21:51:41 +0200 |
|---|---|---|
| committer | Jani Nikula | 2018-05-24 15:15:14 +0200 |
| commit | 84bb2916a6835636fe28e8db192c3293f2d4df21 (patch) | |
| tree | 1860c972135085094eca489a315dc6020e6b61c0 /drivers/gpu/drm/i915/intel_dp.c | |
| parent | drm/i915/psr: Avoid DPCD reads when panel does not support PSR (diff) | |
| download | kernel-qcow2-linux-84bb2916a6835636fe28e8db192c3293f2d4df21.tar.gz kernel-qcow2-linux-84bb2916a6835636fe28e8db192c3293f2d4df21.tar.xz kernel-qcow2-linux-84bb2916a6835636fe28e8db192c3293f2d4df21.zip | |
drm/i915/psr: Check for SET_POWER_CAPABLE bit at PSR init time.
By moving the check from psr_compute_config() to psr_init_dpcd(), we get
to set the dev_priv->psr.sink_support flag only when the panel is
capable of changing power state. An additional benefit is that the check
will be performed only at init time instead of every atomic_check.
This should change the psr_basic IGT failures on HSW to skips.
v2: Return early when SET_POWER_CAPABLE bit is 0 (Jose)
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106217
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106346
Cc: José Roberto de Souza <jose.souza@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20180511195145.3829-2-dhinakaran.pandiyan@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/intel_dp.c')
| -rw-r--r-- | drivers/gpu/drm/i915/intel_dp.c | 8 |
1 files changed, 6 insertions, 2 deletions
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index ce07bd794aed..37b9f62aeb6e 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -3730,8 +3730,6 @@ intel_edp_init_dpcd(struct intel_dp *intel_dp) dev_priv->no_aux_handshake = intel_dp->dpcd[DP_MAX_DOWNSPREAD] & DP_NO_AUX_HANDSHAKE_LINK_TRAINING; - intel_psr_init_dpcd(intel_dp); - /* * Read the eDP display control registers. * @@ -3747,6 +3745,12 @@ intel_edp_init_dpcd(struct intel_dp *intel_dp) DRM_DEBUG_KMS("eDP DPCD: %*ph\n", (int) sizeof(intel_dp->edp_dpcd), intel_dp->edp_dpcd); + /* + * This has to be called after intel_dp->edp_dpcd is filled, PSR checks + * for SET_POWER_CAPABLE bit in intel_dp->edp_dpcd[1] + */ + intel_psr_init_dpcd(intel_dp); + /* Read the eDP 1.4+ supported link rates. */ if (intel_dp->edp_dpcd[0] >= DP_EDP_14) { __le16 sink_rates[DP_MAX_SUPPORTED_RATES]; |