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| author | Chon Ming Lee | 2014-04-09 12:28:15 +0200 |
|---|---|---|
| committer | Daniel Vetter | 2014-05-12 19:50:12 +0200 |
| commit | 00fc31b72ea773fa966a486e54ca379045bd2cfd (patch) | |
| tree | 822526ba6d94bd360a2890e182913c44fb7a9cc2 /drivers/gpu/drm/i915/intel_drv.h | |
| parent | drm/i915/chv: Add DPIO offset for Cherryview. v3 (diff) | |
| download | kernel-qcow2-linux-00fc31b72ea773fa966a486e54ca379045bd2cfd.tar.gz kernel-qcow2-linux-00fc31b72ea773fa966a486e54ca379045bd2cfd.tar.xz kernel-qcow2-linux-00fc31b72ea773fa966a486e54ca379045bd2cfd.zip | |
drm/i915/chv: Update Cherryview DPLL changes to support Port D. v2
The additional DPLL registers added to support Port D. Besides, add
some new PHY control and status registers based on B-spec.
v2: Based on Ville review
- Corrected DPIO_PHY_STATUS offset and name.
- Rebase based on upstream change after introduce enum dpio_phy and
enum dpio_channel.
v3: Rebased on top of Antti's 3-pipe prep patch. Note that the new offsets for
the DPLL registers aren't in place yet, so this introduces a slight regression.
But since 3 pipe support isn't fully enabled yet anyaway in -internal this
shouldn't matter too much.
Signed-off-by: Chon Ming Lee <chon.ming.lee@intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_drv.h')
| -rw-r--r-- | drivers/gpu/drm/i915/intel_drv.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index d8b540b891d1..9d5816d06b53 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -561,6 +561,7 @@ vlv_dport_to_channel(struct intel_digital_port *dport) { switch (dport->port) { case PORT_B: + case PORT_D: return DPIO_CH0; case PORT_C: return DPIO_CH1; |