diff options
| author | Mika Kuoppala | 2018-03-20 16:17:33 +0100 |
|---|---|---|
| committer | Mika Kuoppala | 2018-03-23 10:21:14 +0100 |
| commit | 66c1f77ae2b773f349c1ea1312d69a6ab775cc26 (patch) | |
| tree | 59c6baa69abfc8bb38cadca34163d73ee410c4a3 /drivers/gpu/drm/i915/intel_pm.c | |
| parent | drm/i915: Flush pending interrupt following a GPU reset (diff) | |
| download | kernel-qcow2-linux-66c1f77ae2b773f349c1ea1312d69a6ab775cc26.tar.gz kernel-qcow2-linux-66c1f77ae2b773f349c1ea1312d69a6ab775cc26.tar.xz kernel-qcow2-linux-66c1f77ae2b773f349c1ea1312d69a6ab775cc26.zip | |
drm/i915: Avoid setting ring freq on invalid rps freqs
Looping through rps frequencies when both min and max are zero
ends up into an endless loop. This can happen during hardware
enablement.
Bail out early if rps frequencies are not correctly set yet.
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/20180320151734.11761-1-mika.kuoppala@linux.intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/intel_pm.c')
| -rw-r--r-- | drivers/gpu/drm/i915/intel_pm.c | 9 |
1 files changed, 6 insertions, 3 deletions
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index dd5ddb77b306..19e82aaa9863 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -6890,15 +6890,18 @@ static void gen6_enable_rps(struct drm_i915_private *dev_priv) static void gen6_update_ring_freq(struct drm_i915_private *dev_priv) { struct intel_rps *rps = &dev_priv->gt_pm.rps; - int min_freq = 15; + const int min_freq = 15; + const int scaling_factor = 180; unsigned int gpu_freq; unsigned int max_ia_freq, min_ring_freq; unsigned int max_gpu_freq, min_gpu_freq; - int scaling_factor = 180; struct cpufreq_policy *policy; WARN_ON(!mutex_is_locked(&dev_priv->pcu_lock)); + if (rps->max_freq <= rps->min_freq) + return; + policy = cpufreq_cpu_get(0); if (policy) { max_ia_freq = policy->cpuinfo.max_freq; @@ -6932,7 +6935,7 @@ static void gen6_update_ring_freq(struct drm_i915_private *dev_priv) * the PCU should use as a reference to determine the ring frequency. */ for (gpu_freq = max_gpu_freq; gpu_freq >= min_gpu_freq; gpu_freq--) { - int diff = max_gpu_freq - gpu_freq; + const int diff = max_gpu_freq - gpu_freq; unsigned int ia_freq = 0, ring_freq = 0; if (IS_GEN9_BC(dev_priv) || IS_CANNONLAKE(dev_priv)) { |