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| author | Rodrigo Vivi | 2018-03-07 23:09:12 +0100 |
|---|---|---|
| committer | Rodrigo Vivi | 2018-03-08 00:54:31 +0100 |
| commit | a4713c5a8d612b4a3445874a9eb8af5a92c08bd0 (patch) | |
| tree | 40e5832207e534e75bfed406fc94a8508616c35b /drivers/gpu/drm/i915/intel_pm.c | |
| parent | drm/i915/icl: Gen11 forcewake support (diff) | |
| download | kernel-qcow2-linux-a4713c5a8d612b4a3445874a9eb8af5a92c08bd0.tar.gz kernel-qcow2-linux-a4713c5a8d612b4a3445874a9eb8af5a92c08bd0.tar.xz kernel-qcow2-linux-a4713c5a8d612b4a3445874a9eb8af5a92c08bd0.zip | |
drm/i915/cnl: Add Wa_2201832410
"Clock gating bug in GWL may not clear barrier state when an EOT
is received, causing a hang the next time that barrier is used."
HSDES: 2201832410
Cc: Rafael Antognolli <rafael.antognolli@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20180307220912.3681-1-rodrigo.vivi@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/intel_pm.c')
| -rw-r--r-- | drivers/gpu/drm/i915/intel_pm.c | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 6cab20ce167a..b8da4dcdd584 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -8522,6 +8522,11 @@ static void cnl_init_clock_gating(struct drm_i915_private *dev_priv) val |= SARBUNIT_CLKGATE_DIS; I915_WRITE(SLICE_UNIT_LEVEL_CLKGATE, val); + /* Wa_2201832410:cnl */ + val = I915_READ(SUBSLICE_UNIT_LEVEL_CLKGATE); + val |= GWUNIT_CLKGATE_DIS; + I915_WRITE(SUBSLICE_UNIT_LEVEL_CLKGATE, val); + /* WaDisableVFclkgate:cnl */ /* WaVFUnitClockGatingDisable:cnl */ val = I915_READ(UNSLICE_UNIT_LEVEL_CLKGATE); |