diff options
| author | Ville Syrjälä | 2013-12-05 14:51:29 +0100 |
|---|---|---|
| committer | Daniel Vetter | 2013-12-17 13:17:51 +0100 |
| commit | a68d68eebc9820212186b6d02f2dce09deef0e53 (patch) | |
| tree | 4b31a0c11d1c8406cd0e304c3b7ae0f26097a545 /drivers/gpu/drm/i915/intel_pm.c | |
| parent | drm/i915: Add IVB DDB partitioning control (diff) | |
| download | kernel-qcow2-linux-a68d68eebc9820212186b6d02f2dce09deef0e53.tar.gz kernel-qcow2-linux-a68d68eebc9820212186b6d02f2dce09deef0e53.tar.xz kernel-qcow2-linux-a68d68eebc9820212186b6d02f2dce09deef0e53.zip | |
drm/i915: Add ILK/SNB/IVB WM latency field support
Add a new function ilk_wm_lp_latency() which will tell us what to write
into the WM_LPx register latency field. HSW is different from erlier
gens in this regard.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_pm.c')
| -rw-r--r-- | drivers/gpu/drm/i915/intel_pm.c | 13 |
1 files changed, 12 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index be8244282742..dbd025a4f22f 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -2715,6 +2715,17 @@ static int ilk_wm_lp_to_level(int wm_lp, const struct intel_pipe_wm *pipe_wm) return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable); } +/* The value we need to program into the WM_LPx latency field */ +static unsigned int ilk_wm_lp_latency(struct drm_device *dev, int level) +{ + struct drm_i915_private *dev_priv = dev->dev_private; + + if (IS_HASWELL(dev)) + return 2 * level; + else + return dev_priv->wm.pri_latency[level]; +} + static void hsw_compute_wm_results(struct drm_device *dev, const struct intel_pipe_wm *merged, enum intel_ddb_partitioning partitioning, @@ -2737,7 +2748,7 @@ static void hsw_compute_wm_results(struct drm_device *dev, break; results->wm_lp[wm_lp - 1] = WM3_LP_EN | - ((level * 2) << WM1_LP_LATENCY_SHIFT) | + (ilk_wm_lp_latency(dev, level) << WM1_LP_LATENCY_SHIFT) | (r->pri_val << WM1_LP_SR_SHIFT) | r->cur_val; |