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| author | Jesse Barnes | 2013-03-08 19:45:51 +0100 |
|---|---|---|
| committer | Daniel Vetter | 2013-03-23 12:18:00 +0100 |
| commit | d3bc03030a3994181d420e9f3b858fe6edd71839 (patch) | |
| tree | 946b30a135b2460cb78607945d5efe25b7029106 /drivers/gpu/drm/i915/intel_pm.c | |
| parent | drm/i915: add more VLV IDs (diff) | |
| download | kernel-qcow2-linux-d3bc03030a3994181d420e9f3b858fe6edd71839.tar.gz kernel-qcow2-linux-d3bc03030a3994181d420e9f3b858fe6edd71839.tar.xz kernel-qcow2-linux-d3bc03030a3994181d420e9f3b858fe6edd71839.zip | |
drm/i915: fix WaDisablePSDDualDispatchEnable on VLV v2
Can prevent a hang when we get to tessellation. We need to set bit 15
as well for this workaround.
v2: update changelog with accurate info
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_pm.c')
| -rw-r--r-- | drivers/gpu/drm/i915/intel_pm.c | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 52d4f2d660db..0bb94d963b0a 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -3899,8 +3899,10 @@ static void valleyview_init_clock_gating(struct drm_device *dev) CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE | CHICKEN3_DGMG_DONE_FIX_DISABLE); + /* WaDisablePSDDualDispatchEnable */ I915_WRITE(GEN7_HALF_SLICE_CHICKEN1, - _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE)); + _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP | + GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE)); /* Apply the WaDisableRHWOOptimizationForRenderHang workaround. */ I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1, |