diff options
| author | José Roberto de Souza | 2018-06-26 22:16:40 +0200 |
|---|---|---|
| committer | Dhinakaran Pandiyan | 2018-06-27 02:00:14 +0200 |
| commit | 42f53ffcad7fcf11b5767767dd0c0ff607d99787 (patch) | |
| tree | a12ced554c7e5d13d4965dd44d9d0c88298d0fcf /drivers/gpu/drm/i915/intel_psr.c | |
| parent | drm/i915/psr: Warn for erroneous enabling of both PSR1 and PSR2. (diff) | |
| download | kernel-qcow2-linux-42f53ffcad7fcf11b5767767dd0c0ff607d99787.tar.gz kernel-qcow2-linux-42f53ffcad7fcf11b5767767dd0c0ff607d99787.tar.xz kernel-qcow2-linux-42f53ffcad7fcf11b5767767dd0c0ff607d99787.zip | |
drm/i915/psr: Remove intel_crtc_state parameter from disable_source()
It was only used in VLV/CHV so after the removal of the PSR support
for those platforms it is not necessary any more.
v7: Rebased
Reviewed-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20180626201644.21932-1-jose.souza@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/intel_psr.c')
| -rw-r--r-- | drivers/gpu/drm/i915/intel_psr.c | 5 |
1 files changed, 2 insertions, 3 deletions
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c index 1b439629cb66..f6d384a11b79 100644 --- a/drivers/gpu/drm/i915/intel_psr.c +++ b/drivers/gpu/drm/i915/intel_psr.c @@ -625,8 +625,7 @@ unlock: } static void -intel_psr_disable_source(struct intel_dp *intel_dp, - const struct intel_crtc_state *old_crtc_state) +intel_psr_disable_source(struct intel_dp *intel_dp) { struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); struct drm_device *dev = intel_dig_port->base.base.dev; @@ -693,7 +692,7 @@ void intel_psr_disable(struct intel_dp *intel_dp, return; } - intel_psr_disable_source(intel_dp, old_crtc_state); + intel_psr_disable_source(intel_dp); /* Disable PSR on Sink */ drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, 0); |